board/mpc8540ads/init.S

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3 * Copyright (C) 2002,2003, Motorola Inc.
   4 * Xianghua Xiao <X.Xiao@motorola.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25 #include <ppc_asm.tmpl>
  26 #include <ppc_defs.h>
  27 #include <asm/cache.h>
  28 #include <asm/mmu.h>
  29 #include <config.h>
  30 #include <mpc85xx.h>
  31
  32 #define entry_start \
  33         mflr    r1      ;       \
  34         bl      0f      ;
  35
  36 #define entry_end \
  37 0:      mflr    r0      ;       \
  38         mtlr    r1      ;       \
  39         blr             ;
  40
  41 /* TLB1 entries configuration: */
  42
  43         .section        .bootpg, "ax"
  44         .globl  tlb1_entry
  45 tlb1_entry:
  46         entry_start
  47
  48         .long 0x0a      /* the following data table uses a few of 16 TLB entries */
  49
  50         .long TLB1_MAS0(1,1,0)
  51         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
  52         .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  53         .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  54
  55   #if defined(CFG_FLASH_PORT_WIDTH_16)
  56         .long TLB1_MAS0(1,2,0)
  57         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
  58         .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  59         .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  60
  61         .long TLB1_MAS0(1,3,0)
  62         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
  63         .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
  64         .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
  65   #else
  66         .long TLB1_MAS0(1,2,0)
  67         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
  68         .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  69         .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  70
  71         .long TLB1_MAS0(1,3,0)
  72         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  73         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
  74         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  75   #endif
  76
  77   #if !defined(CONFIG_SPD_EEPROM)
  78         .long TLB1_MAS0(1,4,0)
  79         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
  80         .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
  81         .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  82
  83         .long TLB1_MAS0(1,5,0)
  84         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
  85         .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
  86         .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  87   #else
  88         .long TLB1_MAS0(1,4,0)
  89         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  90         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
  91         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  92
  93         .long TLB1_MAS0(1,5,0)
  94         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  95         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
  96         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
  97   #endif
  98
  99         .long TLB1_MAS0(1,6,0)
 100         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
 101   #if defined(CONFIG_RAM_AS_FLASH)
 102         .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 103   #else
 104         .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
 105   #endif
 106         .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 107
 108         .long TLB1_MAS0(1,7,0)
 109         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
 110   #ifdef CONFIG_L2_INIT_RAM
 111         .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
 112   #else
 113         .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
 114   #endif
 115         .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 116
 117         .long TLB1_MAS0(1,8,0)
 118         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 119         .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 120         .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 121
 122         .long TLB1_MAS0(1,9,0)
 123         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
 124         .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 125         .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 126
 127   #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
 128         .long TLB1_MAS0(1,15,0)
 129         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
 130         .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 131         .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 132   #else
 133         .long TLB1_MAS0(1,15,0)
 134         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
 135         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
 136         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
 137   #endif
 138         entry_end
 139
 140 /*
 141  * LAW(Local Access Window) configuration:
 142  *
 143  * 0x0000_0000     0x7fff_ffff     DDR                     2G
 144  * 0x8000_0000     0x9fff_ffff     PCI MEM                 512M
 145  * 0xe000_0000     0xe000_ffff     CCSR                    1M
 146  * 0xe200_0000     0xe2ff_ffff     PCI IO                  16M
 147  * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
 148  * 0xf800_0000     0xf80f_ffff     BCSR                    1M
 149  * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
 150  *
 151  * Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 152  * Note: If flash is 8M at default position(last 8M),no LAW needed.
 153  */
 154
 155 #if !defined(CONFIG_SPD_EEPROM)
 156 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
 157 #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
 158 #else
 159 #define LAWBAR0 0
 160 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 161 #endif
 162
 163 #define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
 164 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 165
 166 /*
 167  * This is not so much the SDRAM map as it is the whole localbus map.
 168  */
 169 #if !defined(CONFIG_RAM_AS_FLASH)
 170 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 171 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 172 #else
 173 #define LAWBAR2 0
 174 #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 175 #endif
 176
 177 #define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff)
 178 #define LAWAR3  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
 179
 180 /*
 181  * Rapid IO at 0xc000_0000 for 512 M
 182  */
 183 #define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff)
 184 #define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 185
 186
 187         .section .bootpg, "ax"
 188         .globl  law_entry
 189 law_entry:
 190         entry_start
 191         .long 0x05
 192         .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
 193         .long LAWBAR4,LAWAR4
 194         entry_end