2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/mpc8349_pci.h>
35 #ifdef CONFIG_SPD_EEPROM
36 #include <spd_sdram.h>
40 #if defined(CONFIG_OF_FLAT_TREE)
44 #ifndef CONFIG_SPD_EEPROM
45 /*************************************************************************
46 * fixed sdram init -- doesn't use serial presence detect.
47 ************************************************************************/
50 volatile immap_t *im = (immap_t *) CFG_IMMR;
51 u32 ddr_size; /* The size of RAM, in bytes */
52 u32 ddr_size_log2 = 0;
54 for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
61 im->sysconf.ddrlaw[0].ar =
62 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
63 im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
65 /* Only one CS0 for DDR */
66 im->ddr.csbnds[0].csbnds = 0x0000000f;
67 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
69 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
70 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
72 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
73 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
75 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
76 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
77 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
79 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
80 im->ddr.sdram_interval =
81 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
82 SDRAM_INTERVAL_BSTOPRE_SHIFT);
83 im->ddr.sdram_clk_cntl =
84 DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
88 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
90 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
91 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
92 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
93 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
94 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
102 * Initialize PCI Devices, report devices found
104 #ifndef CONFIG_PCI_PNP
105 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
113 pci_cfgfunc_config_device,
117 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
123 volatile static struct pci_controller hose[] = {
125 #ifndef CONFIG_PCI_PNP
126 config_table:pci_mpc83xxmitx_config_table,
130 #ifndef CONFIG_PCI_PNP
131 config_table:pci_mpc83xxmitx_config_table,
135 #endif /* CONFIG_PCI */
137 /* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */
139 void sdram_init(void)
141 volatile immap_t *immap = (immap_t *) CFG_IMMR;
142 volatile lbus83xx_t *lbc = &immap->lbus;
144 #if defined(CFG_BR2_PRELIM) \
145 && defined(CFG_OR2_PRELIM) \
146 && defined(CFG_LBLAWBAR2_PRELIM) \
147 && defined(CFG_LBLAWAR2_PRELIM) \
148 && !defined(CONFIG_COMPACT_FLASH)
150 uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
152 puts("\n SDRAM on Local Bus: ");
153 print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
156 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
159 /*setup mtrpt, lsrt and lbcr for LB bus */
160 lbc->lbcr = CFG_LBC_LBCR;
161 lbc->mrtpr = CFG_LBC_MRTPR;
162 lbc->lsrt = CFG_LBC_LSRT;
166 * Configure the SDRAM controller Machine Mode register.
168 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
170 lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */
175 lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */
177 *sdram_addr = 0xff; /*1 time*/
179 *sdram_addr = 0xff; /*2 times*/
181 *sdram_addr = 0xff; /*3 times*/
183 *sdram_addr = 0xff; /*4 times*/
185 *sdram_addr = 0xff; /*5 times*/
187 *sdram_addr = 0xff; /*6 times*/
189 *sdram_addr = 0xff; /*7 times*/
191 *sdram_addr = 0xff; /*8 times*/
194 lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */
199 lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */
205 puts("SDRAM on Local Bus is NOT available!\n");
207 #ifdef CFG_BR2_PRELIM
208 lbc->bank[2].br = CFG_BR2_PRELIM;
209 lbc->bank[2].or = CFG_OR2_PRELIM;
212 #ifdef CFG_BR3_PRELIM
213 lbc->bank[3].br = CFG_BR3_PRELIM;
214 lbc->bank[3].or = CFG_OR3_PRELIM;
219 long int initdram(int board_type)
221 volatile immap_t *im = (immap_t *) CFG_IMMR;
223 #ifdef CONFIG_DDR_ECC
224 volatile ddr83xx_t *ddr = &im->ddr;
227 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
230 /* DDR SDRAM - Main SODIMM */
231 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
232 #ifdef CONFIG_SPD_EEPROM
235 msize = fixed_sdram();
238 #ifdef CONFIG_DDR_ECC
239 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
240 /* Unlike every other board, on the 83xx spd_sdram() returns
241 megabytes instead of just bytes. That's why we need to
242 multiple by 1MB when calling ddr_enable_ecc(). */
243 ddr_enable_ecc(msize * 1048576);
247 * Initialize SDRAM if it is on local bus.
251 /* return total bus SDRAM size(bytes) -- DDR */
252 return msize * 1024 * 1024;
257 puts("Board: Freescale MPC8349E-mITX\n");
263 * Implement a work-around for a hardware problem with compact
266 * Program the UPM if compact flash is enabled.
268 int misc_init_f(void)
270 volatile u32 *vsc7385_cpuctrl;
272 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
273 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
274 means it is 0 when the IRQ is not active. This makes the wire-AND
275 logic always assert IRQ7 to CPU even if there is no request from the
276 switch. Since the compact flash and the switch share the same IRQ,
277 the Linux kernel will think that the compact flash is requesting irq
278 and get stuck when it tries to clear the IRQ. Thus we need to set
279 the L2_IRQ0 and L2_IRQ1 to active low.
281 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
282 Without this code, compact flash will not work in Linux because
283 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
284 don't enable compact flash for U-Boot.
287 vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0);
288 *vsc7385_cpuctrl |= 0x0c;
290 #ifdef CONFIG_COMPACT_FLASH
291 /* UPM Table Configuration Code */
292 static uint UPMATable[] = {
293 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
294 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
295 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
296 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
297 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
298 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
299 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
300 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
301 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
302 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
303 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
304 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
305 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
306 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
307 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
308 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
310 volatile immap_t *immap = (immap_t *) CFG_IMMR;
311 volatile lbus83xx_t *lbus = &immap->lbus;
313 lbus->bank[3].br = CFG_BR3_PRELIM;
314 lbus->bank[3].or = CFG_OR3_PRELIM;
316 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
317 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
319 lbus->mamr = 0x08404440;
321 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
323 puts("UPMA: Configured for compact flash\n");
330 * Make sure the EEPROM has the HRCW correctly programmed.
331 * Make sure the RTC is correctly programmed.
333 * The MPC8349E-mITX can be configured to load the HRCW from
334 * EEPROM instead of flash. This is controlled via jumpers
335 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
336 * jumpered), but if they're set to 001 or 010, then the HRCW is
337 * read from the "I2C EEPROM".
339 * This function makes sure that the I2C EEPROM is programmed
342 int misc_init_r(void)
346 #ifdef CONFIG_HARD_I2C
348 unsigned int orig_bus = i2c_get_bus_num();;
351 #ifdef CFG_I2C_RTC_ADDR
355 #ifdef CFG_I2C_EEPROM_ADDR
356 static u8 eeprom_data[] = /* HRCW data */
359 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00,
360 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00,
363 u8 data[sizeof(eeprom_data)];
366 printf("Board revision: ");
368 if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
369 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
370 else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
371 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
377 #ifdef CFG_I2C_EEPROM_ADDR
380 if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
381 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
383 (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
384 sizeof(eeprom_data)) != 0) {
385 puts("Failure writing the HRCW to EEPROM via I2C.\n");
390 puts("Failure reading the HRCW from EEPROM via I2C.\n");
395 #ifdef CFG_I2C_RTC_ADDR
398 if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
401 /* Work-around for MPC8349E-mITX bug #13601.
402 If the RTC does not contain valid register values, the DS1339
403 Linux driver will not work.
406 /* Make sure status register bits 6-2 are zero */
407 ds1339_data[0x0f] &= ~0x7c;
409 /* Check for a valid day register value */
410 ds1339_data[0x03] &= ~0xf8;
411 if (ds1339_data[0x03] == 0) {
412 ds1339_data[0x03] = 1;
415 /* Check for a valid date register value */
416 ds1339_data[0x04] &= ~0xc0;
417 if ((ds1339_data[0x04] == 0) ||
418 ((ds1339_data[0x04] & 0x0f) > 9) ||
419 (ds1339_data[0x04] >= 0x32)) {
420 ds1339_data[0x04] = 1;
423 /* Check for a valid month register value */
424 ds1339_data[0x05] &= ~0x60;
426 if ((ds1339_data[0x05] == 0) ||
427 ((ds1339_data[0x05] & 0x0f) > 9) ||
428 ((ds1339_data[0x05] >= 0x13)
429 && (ds1339_data[0x05] <= 0x19))) {
430 ds1339_data[0x05] = 1;
433 /* Enable Oscillator and rate select */
434 ds1339_data[0x0e] = 0x1c;
436 /* Work-around for MPC8349E-mITX bug #13330.
437 Ensure that the RTC control register contains the value 0x1c.
438 This affects SATA performance.
442 (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data,
443 sizeof(ds1339_data))) {
444 puts("Failure writing to the RTC via I2C.\n");
448 puts("Failure reading from the RTC via I2C.\n");
453 i2c_set_bus_num(orig_bus);
459 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
461 ft_board_setup(void *blob, bd_t *bd)
467 ft_pci_setup(blob, bd);
469 ft_cpu_setup(blob, bd);
471 p = ft_get_prop(blob, "/memory/reg", &len);
473 *p++ = cpu_to_be32(bd->bi_memstart);
474 *p = cpu_to_be32(bd->bi_memsize);