2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
14 * PCI Configuration space access support for MPC83xx PCI Bridge
21 #if defined(CONFIG_OF_FLAT_TREE)
25 #include <asm/fsl_i2c.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #if defined(CONFIG_PCI)
30 #define PCI_FUNCTION_CONFIG 0x44
31 #define PCI_FUNCTION_CFG_LOCK 0x20
34 * Initialize PCI Devices, report devices found
36 #ifndef CONFIG_PCI_PNP
37 static struct pci_config_table pci_mpc83xxemds_config_table[] = {
39 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
40 pci_cfgfunc_config_device,
43 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
48 static struct pci_controller hose[] = {
50 #ifndef CONFIG_PCI_PNP
51 config_table:pci_mpc83xxemds_config_table,
56 /**********************************************************************
58 *********************************************************************/
59 void pci_init_board(void)
60 #ifdef CONFIG_PCISLAVE
63 volatile immap_t *immr;
64 volatile law83xx_t *pci_law;
65 volatile pot83xx_t *pci_pot;
66 volatile pcictrl83xx_t *pci_ctrl;
67 volatile pciconf83xx_t *pci_conf;
69 immr = (immap_t *) CFG_IMMR;
70 pci_law = immr->sysconf.pcilaw;
71 pci_pot = immr->ios.pot;
72 pci_ctrl = immr->pci_ctrl;
73 pci_conf = immr->pci_conf;
75 * Configure PCI Inbound Translation Windows
77 pci_ctrl[0].pitar0 = 0x0;
78 pci_ctrl[0].pibar0 = 0x0;
79 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
80 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
82 pci_ctrl[0].pitar1 = 0x0;
83 pci_ctrl[0].pibar1 = 0x0;
84 pci_ctrl[0].piebar1 = 0x0;
85 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
87 pci_ctrl[0].pitar2 = 0x0;
88 pci_ctrl[0].pibar2 = 0x0;
89 pci_ctrl[0].piebar2 = 0x0;
90 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
92 hose[0].first_busno = 0;
93 hose[0].last_busno = 0xff;
94 pci_setup_indirect(&hose[0],
95 (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
98 pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
100 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
101 pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
105 * Clear non-reserved bits in status register.
107 pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
109 pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
110 PCI_LATENCY_TIMER, 0x80);
113 * Unlock configuration lock in PCI function configuration register.
115 pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
116 PCI_FUNCTION_CONFIG, ®16);
117 reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
118 pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
119 PCI_FUNCTION_CONFIG, reg16);
121 printf("Enabled PCI 32bit Agent Mode\n");
125 volatile immap_t *immr;
126 volatile clk83xx_t *clk;
127 volatile law83xx_t *pci_law;
128 volatile pot83xx_t *pci_pot;
129 volatile pcictrl83xx_t *pci_ctrl;
130 volatile pciconf83xx_t *pci_conf;
132 u8 val8, orig_i2c_bus;
137 immr = (immap_t *) CFG_IMMR;
138 clk = (clk83xx_t *) & immr->clk;
139 pci_law = immr->sysconf.pcilaw;
140 pci_pot = immr->ios.pot;
141 pci_ctrl = immr->pci_ctrl;
142 pci_conf = immr->pci_conf;
144 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
149 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
150 printf("PCI clock is 66MHz\n");
151 #elif defined(PCI_33M)
152 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
153 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
154 printf("PCI clock is 33MHz\n");
156 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
157 printf("PCI clock is 66MHz\n");
162 * Configure PCI Local Access Windows
164 pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
165 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
167 pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
168 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
171 * Configure PCI Outbound Translation Windows
174 /* PCI mem space - prefetch */
175 pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
176 pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
178 POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
180 /* PCI mmio - non-prefetch mem space */
181 pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
182 pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
183 pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
186 pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
187 pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
188 pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
191 * Configure PCI Inbound Translation Windows
193 pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
194 pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
195 pci_ctrl[0].piebar1 = 0x0;
197 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
201 * Assign PIB PMC slot to desired PCI bus
204 /* Switch temporarily to I2C bus #2 */
205 orig_i2c_bus = i2c_get_bus_num();
209 i2c_write(0x23, 0x6, 1, &val8, 1);
210 i2c_write(0x23, 0x7, 1, &val8, 1);
212 i2c_write(0x23, 0x2, 1, &val8, 1);
213 i2c_write(0x23, 0x3, 1, &val8, 1);
216 i2c_write(0x26, 0x6, 1, &val8, 1);
218 i2c_write(0x26, 0x7, 1, &val8, 1);
220 val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
221 i2c_write(0x26, 0x2, 1, &val8, 1);
223 i2c_write(0x26, 0x3, 1, &val8, 1);
226 i2c_write(0x27, 0x6, 1, &val8, 1);
227 i2c_write(0x27, 0x7, 1, &val8, 1);
229 i2c_write(0x27, 0x2, 1, &val8, 1);
231 i2c_write(0x27, 0x3, 1, &val8, 1);
234 /* Reset to original I2C bus */
235 i2c_set_bus_num(orig_i2c_bus);
238 * Release PCI RST Output signal
244 hose[0].first_busno = 0;
245 hose[0].last_busno = 0xff;
247 /* PCI memory prefetch space */
248 pci_set_region(hose[0].regions + 0,
251 CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
253 /* PCI memory space */
254 pci_set_region(hose[0].regions + 1,
256 CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
259 pci_set_region(hose[0].regions + 2,
261 CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
263 /* System memory space */
264 pci_set_region(hose[0].regions + 3,
265 CFG_PCI_SLV_MEM_LOCAL,
267 CFG_PCI_SLV_MEM_SIZE,
268 PCI_REGION_MEM | PCI_REGION_MEMORY);
270 hose[0].region_count = 4;
272 pci_setup_indirect(&hose[0],
273 (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
275 pci_register_hose(hose);
278 * Write command register
281 dev = PCI_BDF(0, 0, 0);
282 pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16);
283 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
284 pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
287 * Clear non-reserved bits in status register.
289 pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
290 pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
291 pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
293 printf("PCI 32bit bus on PMC2 & PMC3\n");
298 hose->last_busno = pci_hose_scan(hose);
300 #endif /* CONFIG_PCISLAVE */
302 #ifdef CONFIG_OF_FLAT_TREE
304 ft_pci_setup(void *blob, bd_t *bd)
309 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
311 p[0] = hose[0].first_busno;
312 p[1] = hose[0].last_busno;
315 #endif /* CONFIG_OF_FLAT_TREE */
316 #endif /* CONFIG_PCI */