2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
22 #if defined(CONFIG_PCI)
25 #if defined(CONFIG_SPD_EEPROM)
26 #include <spd_sdram.h>
30 #if defined(CONFIG_OF_FLAT_TREE)
34 const qe_iop_conf_t qe_iop_conf_tab[] = {
36 {1, 0, 1, 0, 1}, /* TxD0 */
37 {1, 1, 1, 0, 1}, /* TxD1 */
38 {1, 2, 1, 0, 1}, /* TxD2 */
39 {1, 3, 1, 0, 1}, /* TxD3 */
40 {1, 9, 1, 0, 1}, /* TxER */
41 {1, 12, 1, 0, 1}, /* TxEN */
42 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
44 {1, 4, 2, 0, 1}, /* RxD0 */
45 {1, 5, 2, 0, 1}, /* RxD1 */
46 {1, 6, 2, 0, 1}, /* RxD2 */
47 {1, 7, 2, 0, 1}, /* RxD3 */
48 {1, 8, 2, 0, 1}, /* RxER */
49 {1, 10, 2, 0, 1}, /* RxDV */
50 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
51 {1, 11, 2, 0, 1}, /* COL */
52 {1, 13, 2, 0, 1}, /* CRS */
55 {1, 18, 1, 0, 1}, /* TxD0 */
56 {1, 19, 1, 0, 1}, /* TxD1 */
57 {1, 20, 1, 0, 1}, /* TxD2 */
58 {1, 21, 1, 0, 1}, /* TxD3 */
59 {1, 27, 1, 0, 1}, /* TxER */
60 {1, 30, 1, 0, 1}, /* TxEN */
61 {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
63 {1, 22, 2, 0, 1}, /* RxD0 */
64 {1, 23, 2, 0, 1}, /* RxD1 */
65 {1, 24, 2, 0, 1}, /* RxD2 */
66 {1, 25, 2, 0, 1}, /* RxD3 */
67 {1, 26, 1, 0, 1}, /* RxER */
68 {1, 28, 2, 0, 1}, /* Rx_DV */
69 {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
70 {1, 29, 2, 0, 1}, /* COL */
71 {1, 31, 2, 0, 1}, /* CRS */
73 {3, 4, 3, 0, 2}, /* MDIO */
74 {3, 5, 1, 0, 2}, /* MDC */
76 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
79 int board_early_init_f(void)
81 volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
83 /* Enable flash write */
89 int fixed_sdram(void);
91 long int initdram(int board_type)
93 volatile immap_t *im = (immap_t *) CFG_IMMR;
96 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
99 /* DDR SDRAM - Main SODIMM */
100 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
102 msize = fixed_sdram();
104 puts("\n DDR RAM: ");
106 /* return total bus SDRAM size(bytes) -- DDR */
107 return (msize * 1024 * 1024);
110 /*************************************************************************
111 * fixed sdram init -- doesn't use serial presence detect.
112 ************************************************************************/
113 int fixed_sdram(void)
115 volatile immap_t *im = (immap_t *) CFG_IMMR;
120 msize = CFG_DDR_SIZE;
121 for (ddr_size = msize << 20, ddr_size_log2 = 0;
122 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
127 im->sysconf.ddrlaw[0].ar =
128 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
129 #if (CFG_DDR_SIZE != 128)
130 #warning Currenly any ddr size other than 128 is not supported
132 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
133 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
134 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
135 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
136 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
137 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
138 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
139 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
140 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
141 im->ddr.sdram_mode = CFG_DDR_MODE;
142 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
143 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
144 __asm__ __volatile__ ("sync");
147 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
148 __asm__ __volatile__ ("sync");
154 puts("Board: Freescale MPC832XEMDS\n");
158 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
160 ft_board_setup(void *blob, bd_t *bd)
166 ft_pci_setup(blob, bd);
168 ft_cpu_setup(blob, bd);
170 p = ft_get_prop(blob, "/memory/reg", &len);
172 *p++ = cpu_to_be32(bd->bi_memstart);
173 *p = cpu_to_be32(bd->bi_memsize);