2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
12 * (C) Copyright 2003-2004 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm/m8260_pci.h>
44 * I/O Port configuration table
46 * if conf is 1, then that port pin will be configured at boot time
47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 #define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
51 #define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
52 #define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
54 const iop_conf_t iop_conf_tab[4][32] = {
56 /* Port A configuration */
57 { /* conf ppar psor pdir podr pdat */
58 /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
59 /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
60 /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
61 /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
62 /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
63 /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
64 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
65 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
66 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
67 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
68 /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
69 /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
70 /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
71 /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
72 /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
73 /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
74 /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
75 /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
76 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
77 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
78 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
79 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
80 /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
81 /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
82 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
83 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
84 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
85 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
86 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
87 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
88 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
89 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
92 /* Port B configuration */
93 { /* conf ppar psor pdir podr pdat */
94 /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
95 /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
96 /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
97 /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
98 /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
99 /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
100 /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
101 /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
102 /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
103 /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
104 /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
105 /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
106 /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
107 /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
108 /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
109 /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
110 /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
111 /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
112 /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
113 /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
114 /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
118 /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
122 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
129 { /* conf ppar psor pdir podr pdat */
130 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
131 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
132 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
133 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
134 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
135 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
136 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
137 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
138 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
139 /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
140 /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
141 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
142 #if CONFIG_ADSTYPE == CFG_8272ADS
143 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
144 /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
145 /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
146 /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
148 /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
149 /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
150 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
151 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
152 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
153 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
154 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
155 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
156 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
157 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
158 #if CONFIG_ADSTYPE == CFG_8272ADS
159 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
160 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
162 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
163 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
164 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
165 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
166 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
167 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
168 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
169 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
170 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
171 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
172 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
173 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
177 { /* conf ppar psor pdir podr pdat */
178 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
179 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
180 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
181 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
182 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
183 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
184 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
185 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
186 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
187 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
188 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
189 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
190 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
191 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
192 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
193 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
194 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
195 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
196 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
197 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
198 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
199 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
200 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
201 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
202 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
203 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
204 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
205 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
206 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
207 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
208 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
209 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
213 void reset_phy (void)
215 vu_long *bcsr = (vu_long *)CFG_BCSR;
218 #if CFG_PHY_ADDR == 0
219 bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
221 bcsr[1] |= FETH1_RST;
223 bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
225 bcsr[3] |= FETH2_RST;
226 #endif /* CFG_PHY_ADDR == 0 */
229 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
231 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
232 * Enable autonegotiation.
234 miiphy_write(CFG_PHY_ADDR, 16, 0x610);
235 miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
238 * Ethernet PHY is configured (by means of configuration pins)
239 * to work at 10Mb/s only. We reconfigure it using MII
240 * to advertise all capabilities, including 100Mb/s, and
241 * restart autonegotiation.
243 miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
244 miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
245 miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
246 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
247 #endif /* CONFIG_MII */
250 int board_early_init_f (void)
252 vu_long *bcsr = (vu_long *)CFG_BCSR;
254 #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
255 bcsr[1] &= ~RS232EN_1;
257 #if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
258 bcsr[1] &= ~RS232EN_2;
261 #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
262 #if CONFIG_ADSTYPE == CFG_PQ2FADS
263 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
264 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
266 volatile immap_t *immap = (immap_t *) CFG_IMMR;
268 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
269 immap->im_siu_conf.sc_siumcr =
270 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
273 #endif /* CONFIG_ADSTYPE != CFG_8260ADS */
278 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
280 long int initdram (int board_type)
282 #if CONFIG_ADSTYPE == CFG_PQ2FADS
284 #elif CONFIG_ADSTYPE == CFG_8272ADS
291 volatile immap_t *immap = (immap_t *) CFG_IMMR;
292 volatile memctl8260_t *memctl = &immap->im_memctl;
293 volatile uchar *ramaddr, c = 0xff;
300 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
301 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
302 immap->im_siu_conf.sc_tescr1 = 0x00004000;
304 memctl->memc_mptpr = CFG_MPTPR;
305 #ifdef CFG_LSDRAM_BASE
307 Initialise local bus SDRAM only if the pins
308 are configured as local bus pins and not as PCI.
309 The configuration is determined by the HRCW.
311 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
312 memctl->memc_lsrt = CFG_LSRT;
313 #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
314 memctl->memc_or3 = 0xFF803280;
315 memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
317 memctl->memc_or4 = 0xFFC01480;
318 memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
319 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
320 memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
321 ramaddr = (uchar *) CFG_LSDRAM_BASE;
323 memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
324 for (i = 0; i < 8; i++)
326 memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
328 memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
330 #endif /* CFG_LSDRAM_BASE */
332 /* Init 60x bus SDRAM */
333 #ifdef CONFIG_SPD_EEPROM
336 uint pbi, bsel, rowst, lsb, tmp;
338 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
340 /* Bank-based interleaving is not supported for physical bank
341 sizes greater than 128MB which is encoded as 0x20 in SPD
343 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
344 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
345 or = ~(msize - 1) << 20; /* SDAM */
346 switch (spd.nbanks) { /* BPD */
359 lsb = 3; /* For 64-bit port, lsb is 3 bits */
361 if (pbi) { /* Bus partition depends on interleaving */
362 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
363 or |= (rowst << 9); /* ROWST */
365 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
366 or |= ((rowst * 2 - 12) << 9); /* ROWST */
368 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
370 psdmr = (pbi << 31); /* PBI */
371 /* Bus multiplexing parameters */
372 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
373 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
374 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
376 tmp = (31 - lsb - 10) - tmp;
377 /* Pin connected to SDA10 is (31 - lsb - 10).
378 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
379 so (rowst + tmp) alternates with AP.
381 if (pbi) /* Table 10-7 */
382 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
384 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
386 /* SDRAM device-specific parameters */
387 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
388 switch (tmp) { /* RFRC */
399 psdmr |= ((tmp - 2) << 15);
404 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
405 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
406 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
408 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
410 switch (i) { /* WRC */
420 /* EAMUX=0 - no external address multiplexing */
421 /* BUFCMD=0 - no external buffers */
422 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
426 switch (spd.refresh & 0x7F) {
445 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
446 ((memctl->memc_mptpr >> 8) + 1)) - 1;
448 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
449 printf ("SPD size: %d\n", spd.info_size);
450 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
451 printf ("Memory type: %d\n", spd.mem_type);
452 printf ("Row addr: %d\n", spd.nrow_addr);
453 printf ("Column addr: %d\n", spd.ncol_addr);
454 printf ("# of rows: %d\n", spd.nrows);
455 printf ("Row density: %d\n", spd.row_dens);
456 printf ("# of banks: %d\n", spd.nbanks);
457 printf ("Data width: %d\n",
458 256 * spd.dataw_msb + spd.dataw_lsb);
459 printf ("Chip width: %d\n", spd.primw);
460 printf ("Refresh rate: %02X\n", spd.refresh);
461 printf ("CAS latencies: %02X\n", spd.cas_lat);
462 printf ("Write latencies: %02X\n", spd.write_lat);
463 printf ("tRP: %d\n", spd.trp);
464 printf ("tRCD: %d\n", spd.trcd);
466 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
467 #endif /* SPD_DEBUG */
469 #else /* !CONFIG_SPD_EEPROM */
473 #endif /* CONFIG_SPD_EEPROM */
474 memctl->memc_psrt = psrt;
475 memctl->memc_or2 = or;
476 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
477 ramaddr = (uchar *) CFG_SDRAM_BASE;
478 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
480 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
481 for (i = 0; i < 8; i++)
484 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
486 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
488 #endif /* CFG_RAMBOOT */
490 /* return total 60x bus SDRAM size */
491 return (msize * 1024 * 1024);
494 int checkboard (void)
496 #if CONFIG_ADSTYPE == CFG_8260ADS
497 puts ("Board: Motorola MPC8260ADS\n");
498 #elif CONFIG_ADSTYPE == CFG_8266ADS
499 puts ("Board: Motorola MPC8266ADS\n");
500 #elif CONFIG_ADSTYPE == CFG_PQ2FADS
501 puts ("Board: Motorola PQ2FADS-ZU\n");
502 #elif CONFIG_ADSTYPE == CFG_8272ADS
503 puts ("Board: Motorola MPC8272ADS\n");
505 puts ("Board: unknown\n");