2 * (C) Copyright 2009-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
27 #include <asm/ppc4xx.h>
32 * This table is used by the cpu boot code to setup the initial tlb
33 * entries. Rather than make broad assumptions in the cpu source tree,
34 * this table lets each board set things up however they like.
36 * Pointer to the table is returned in r1
47 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
48 * use the speed up boot process. It is patched after relocation to
51 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
52 4, AC_RWX | SA_G) /* TLB 0 */
55 * TLB entries for SDRAM are not needed on this platform.
56 * They are dynamically generated in the SPD DDR(2) detection
60 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
63 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
66 tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
67 CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
70 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
72 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
74 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
77 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
79 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
81 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
83 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
85 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
87 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,