2 * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
3 * (C) Copyright 2015 Inter Act B.V.
6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
7 * (C) Copyright 2007-2008
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clk.h>
17 #include <asm/arch/at91sam9g45_matrix.h>
18 #include <asm/arch/at91sam9_smc.h>
19 #include <asm/arch/at91_common.h>
20 #include <asm/arch/at91_pmc.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/clk.h>
24 #include <linux/mtd/nand.h>
25 #include <atmel_lcdc.h>
26 #include <atmel_mci.h>
27 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
32 DECLARE_GLOBAL_DATA_PTR;
34 /* ------------------------------------------------------------------------- */
36 * Miscelaneous platform dependent initialisations
39 #if defined(CONFIG_SPL_BUILD)
42 void at91_spl_board_init(void)
44 #ifdef CONFIG_SYS_USE_MMC
49 #include <asm/arch/atmel_mpddrc.h>
50 static void ddr2_conf(struct atmel_mpddr *ddr2)
52 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
54 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
55 ATMEL_MPDDRC_CR_NR_ROW_14 |
56 ATMEL_MPDDRC_CR_DQMS_SHARED |
57 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
61 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
62 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
63 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
64 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
65 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
66 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
67 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
68 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
70 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
71 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
72 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
73 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
75 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
76 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
77 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
78 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
83 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
84 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
85 struct atmel_mpddr ddr2;
90 /* enable DDR2 clock */
91 writel(AT91_PMC_DDR, &pmc->scer);
93 /* Chip select 1 is for DDR2/SDRAM */
94 csa = readl(&mat->ebicsa);
95 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
96 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
97 writel(csa, &mat->ebicsa);
99 /* DDRAM2 Controller initialize */
100 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
101 ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
105 #ifdef CONFIG_CMD_USB
106 static void picosam9g45_usb_hw_init(void)
108 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
110 writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
112 at91_set_gpio_output(AT91_PIN_PD1, 0);
113 at91_set_gpio_output(AT91_PIN_PD3, 0);
118 static void picosam9g45_macb_hw_init(void)
120 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
121 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
124 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
127 * Disable pull-up on:
128 * RXDV (PA15) => PHY normal mode (not Test mode)
129 * ERX0 (PA12) => PHY ADDR0
130 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
132 * PHY has internal pull-down
134 writel(pin_to_mask(AT91_PIN_PA15) |
135 pin_to_mask(AT91_PIN_PA12) |
136 pin_to_mask(AT91_PIN_PA13),
141 /* Re-enable pull-up */
142 writel(pin_to_mask(AT91_PIN_PA15) |
143 pin_to_mask(AT91_PIN_PA12) |
144 pin_to_mask(AT91_PIN_PA13),
154 vidinfo_t panel_info = {
158 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
159 ATMEL_LCDC_INVFRAME_NORMAL,
164 .vl_right_margin = 1,
166 .vl_upper_margin = 40,
167 .vl_lower_margin = 1,
168 .mmio = ATMEL_BASE_LCDC,
172 void lcd_enable(void)
174 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
177 void lcd_disable(void)
179 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
182 static void picosam9g45_lcd_hw_init(void)
184 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
186 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
187 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
188 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
189 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
190 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
192 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
193 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
194 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
195 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
196 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
197 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
198 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
199 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
200 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
201 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
202 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
203 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
204 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
205 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
206 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
207 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
208 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
209 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
210 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
211 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
212 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
213 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
214 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
215 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
217 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
219 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
222 #ifdef CONFIG_LCD_INFO
226 void lcd_show_board_info(void)
232 lcd_printf("%s\n", U_BOOT_VERSION);
233 lcd_printf("(C) 2015 Inter Act B.V.\n");
234 lcd_printf("support@interact.nl\n");
235 lcd_printf("%s CPU at %s MHz\n",
237 strmhz(temp, get_cpu_clk_rate()));
240 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
241 dram_size += gd->bd->bi_dram[i].size;
242 lcd_printf(" %ld MB SDRAM\n", dram_size >> 20);
244 #endif /* CONFIG_LCD_INFO */
247 #ifdef CONFIG_GENERIC_ATMEL_MCI
248 int board_mmc_init(bd_t *bis)
252 return atmel_mci_init((void *)ATMEL_BASE_MCI0);
256 int board_early_init_f(void)
258 at91_seriald_hw_init();
264 gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
266 /* adress of boot parameters */
267 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
269 #ifdef CONFIG_CMD_USB
270 picosam9g45_usb_hw_init();
272 #ifdef CONFIG_HAS_DATAFLASH
273 at91_spi0_hw_init(1 << 0);
275 #ifdef CONFIG_ATMEL_SPI
276 at91_spi0_hw_init(1 << 4);
279 picosam9g45_macb_hw_init();
282 picosam9g45_lcd_hw_init();
289 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
290 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
295 void dram_init_banksize(void)
297 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
298 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
300 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
301 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
305 #ifdef CONFIG_RESET_PHY_R
311 int board_eth_init(bd_t *bis)
315 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
320 /* SPI chip select control */
321 #ifdef CONFIG_ATMEL_SPI
324 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
326 return bus == 0 && cs < 2;
329 void spi_cs_activate(struct spi_slave *slave)
333 at91_set_gpio_output(AT91_PIN_PB18, 0);
337 at91_set_gpio_output(AT91_PIN_PB3, 0);
342 void spi_cs_deactivate(struct spi_slave *slave)
346 at91_set_gpio_output(AT91_PIN_PB18, 1);
350 at91_set_gpio_output(AT91_PIN_PB3, 1);
354 #endif /* CONFIG_ATMEL_SPI */