2 * Copyright (C) 2006 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/sdram.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/hmatrix.h>
14 #include <asm/arch/mmu.h>
15 #include <asm/arch/portmux.h>
16 #include <atmel_lcdc.h>
19 #include "../../../arch/avr32/cpu/hsmc3.h"
21 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
23 .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
24 .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
25 .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
28 .virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
29 .nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
30 .phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
33 .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
34 .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
35 .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
36 | MMU_VMR_CACHE_WRBACK,
40 #if defined(CONFIG_LCD)
41 /* 480x272x16 @ 72 Hz */
42 vidinfo_t panel_info = {
43 .vl_col = 480, /* Number of columns */
44 .vl_row = 272, /* Number of rows */
45 .vl_clk = 5000000, /* pixel clock in ps */
46 .vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
47 ATMEL_LCDC_INVLINE_INVERTED |
48 ATMEL_LCDC_INVFRAME_INVERTED,
49 .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
50 .vl_tft = 1, /* 0 = passive, 1 = TFT */
51 .vl_hsync_len = 42, /* Length of horizontal sync */
52 .vl_left_margin = 1, /* Time from sync to picture */
53 .vl_right_margin = 1, /* Time from picture to sync */
54 .vl_vsync_len = 1, /* Length of vertical sync */
55 .vl_upper_margin = 12, /* Time from sync to picture */
56 .vl_lower_margin = 1, /* Time from picture to sync */
57 .mmio = LCDC_BASE, /* Memory mapped registers */
64 void lcd_disable(void)
69 DECLARE_GLOBAL_DATA_PTR;
71 static const struct sdram_config sdram_config = {
72 .data_bits = SDRAM_DATA_16BIT,
84 .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
87 int board_early_init_f(void)
89 /* Enable SDRAM in the EBI mux */
90 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
92 /* Enable 26 address bits and NCS2 */
93 portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
94 sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
96 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
98 /* de-assert "force sys reset" pin */
99 portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
100 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
102 /* init custom i/o */
103 /* cpu type inputs */
104 portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
106 /* main board type inputs */
107 portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
109 /* DEBUG input (use weak pullup) */
110 portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
111 PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
113 /* are we suppressing the console ? */
114 if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
115 gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
118 portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
119 portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
120 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
124 /* release phys reset */
125 gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
127 /* setup Data Flash chip select (NCS2) */
128 hsmc3_writel(MODE2, 0x20121003);
129 hsmc3_writel(CYCLE2, 0x000a0009);
130 hsmc3_writel(PULSE2, 0x0a060806);
131 hsmc3_writel(SETUP2, 0x00030102);
133 /* setup FRAM chip select (NCS3) */
134 hsmc3_writel(MODE3, 0x10120001);
135 hsmc3_writel(CYCLE3, 0x001e001d);
136 hsmc3_writel(PULSE3, 0x08040704);
137 hsmc3_writel(SETUP3, 0x02050204);
139 #if defined(CONFIG_MACB)
140 /* init macb0 pins */
141 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
142 portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
145 #if defined(CONFIG_MMC)
146 portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
149 #if defined(CONFIG_LCD)
150 portmux_enable_lcdc(1);
156 int board_early_init_r(void)
158 gd->bd->bi_phy_id[0] = 0x01;
159 gd->bd->bi_phy_id[1] = 0x03;
163 int board_postclk_init(void)
165 /* Use GCLK0 as 10MHz output */
166 gclk_enable_output(0, PORTMUX_DRIVE_LOW);
167 gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
171 /* SPI chip select control */
172 #ifdef CONFIG_ATMEL_SPI
175 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
177 return (bus == 0) && (cs == 0);
180 void spi_cs_activate(struct spi_slave *slave)
184 void spi_cs_deactivate(struct spi_slave *slave)
187 #endif /* CONFIG_ATMEL_SPI */
189 #ifdef CONFIG_CMD_NET
190 int board_eth_init(bd_t *bi)
192 macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
193 macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);