board/menlo/m53menlo/m53menlo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Menlosystems M53Menlo board
   4  *
   5  * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
   6  * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/iomux-mx53.h>
  16 #include <asm/mach-imx/mx5_video.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <asm/gpio.h>
  19 #include <asm/spl.h>
  20 #include <fdt_support.h>
  21 #include <fsl_esdhc.h>
  22 #include <i2c.h>
  23 #include <ipu_pixfmt.h>
  24 #include <linux/errno.h>
  25 #include <linux/fb.h>
  26 #include <mmc.h>
  27 #include <netdev.h>
  28 #include <spl.h>
  29 #include <splash.h>
  30 #include <usb/ehci-ci.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static u32 mx53_dram_size[2];
  35
  36 ulong board_get_usable_ram_top(ulong total_size)
  37 {
  38         /*
  39          * WARNING: We must override get_effective_memsize() function here
  40          * to report only the size of the first DRAM bank. This is to make
  41          * U-Boot relocator place U-Boot into valid memory, that is, at the
  42          * end of the first DRAM bank. If we did not override this function
  43          * like so, U-Boot would be placed at the address of the first DRAM
  44          * bank + total DRAM size - sizeof(uboot), which in the setup where
  45          * each DRAM bank contains 512MiB of DRAM would result in placing
  46          * U-Boot into invalid memory area close to the end of the first
  47          * DRAM bank.
  48          */
  49         return PHYS_SDRAM_2 + mx53_dram_size[1];
  50 }
  51
  52 int dram_init(void)
  53 {
  54         mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  55         mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  56
  57         gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  58
  59         return 0;
  60 }
  61
  62 int dram_init_banksize(void)
  63 {
  64         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  65         gd->bd->bi_dram[0].size = mx53_dram_size[0];
  66
  67         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  68         gd->bd->bi_dram[1].size = mx53_dram_size[1];
  69
  70         return 0;
  71 }
  72
  73 static void setup_iomux_uart(void)
  74 {
  75         static const iomux_v3_cfg_t uart_pads[] = {
  76                 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  77                 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  78         };
  79
  80         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  81 }
  82
  83 static void setup_iomux_fec(void)
  84 {
  85         static const iomux_v3_cfg_t fec_pads[] = {
  86                 /* MDIO pads */
  87                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  88                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  89                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  90
  91                 /* FEC 0 pads */
  92                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  93                              PAD_CTL_HYS | PAD_CTL_PKE),
  94                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  95                              PAD_CTL_HYS | PAD_CTL_PKE),
  96                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97                              PAD_CTL_HYS | PAD_CTL_PKE),
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  99                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100                              PAD_CTL_HYS | PAD_CTL_PKE),
 101                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 102                              PAD_CTL_HYS | PAD_CTL_PKE),
 103                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 104                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 105
 106                 /* FEC 1 pads */
 107                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 108                              PAD_CTL_HYS | PAD_CTL_PKE),
 109                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 110                              PAD_CTL_HYS | PAD_CTL_PKE),
 111                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 112                              PAD_CTL_HYS | PAD_CTL_PKE),
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 114                              PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 116                              PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 118                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 119                              PAD_CTL_HYS | PAD_CTL_PKE),
 120                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 121         };
 122
 123         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 124 }
 125
 126 #ifdef CONFIG_VIDEO
 127 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 128 {
 129         static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 130         int ret;
 131
 132         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 133         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 134
 135         /*
 136          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 137          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 138          */
 139         ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
 140         if (ret)
 141                 puts("IPU:   Failed to configure LDB clock\n");
 142
 143         /* Configure CCM_CSCMR2 */
 144         clrsetbits_le32(&mxc_ccm->cscmr2,
 145                         (0x7 << 26) | BIT(10) | BIT(8),
 146                         (0x5 << 26) | BIT(10) | BIT(8));
 147
 148         /* Configure LDB_CTRL */
 149         writel(0x201, 0x53fa8008);
 150 }
 151
 152 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
 153 {
 154         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 155
 156         /* For ETM0430G0DH6 model, this must be enabled before the clock. */
 157         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 158
 159         /*
 160          * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
 161          * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 162          */
 163         enable_lvds_clock(dev, 63);
 164 }
 165
 166 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
 167 {
 168         gpio_request(IMX_GPIO_NR(6, 0), "LCD");
 169
 170         /*
 171          * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
 172          * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
 173          */
 174         enable_lvds_clock(dev, 233);
 175
 176         /* For ETM0700G0DH6 model, this may be enabled after the clock. */
 177         gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
 178 }
 179
 180 static const char *lvds_compat_string;
 181
 182 static int detect_lvds(struct display_info_t const *dev)
 183 {
 184         u8 touchid[23];
 185         u8 *touchptr = &touchid[0];
 186         int ret;
 187
 188         ret = i2c_set_bus_num(0);
 189         if (ret)
 190                 return 0;
 191
 192         /* Touchscreen is at address 0x38, ID register is 0xbb. */
 193         ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
 194         if (ret)
 195                 return 0;
 196
 197         /* EP0430 prefixes the response with 0xbb, skip it. */
 198         if (*touchptr == 0xbb)
 199                 touchptr++;
 200
 201         /* Skip the 'EP' prefix. */
 202         touchptr += 2;
 203
 204         ret = !memcmp(touchptr, &dev->mode.name[7], 4);
 205         if (ret)
 206                 lvds_compat_string = dev->mode.name;
 207
 208         return ret;
 209 }
 210
 211 void board_preboot_os(void)
 212 {
 213         /* Power off the LCD to prevent awful color flicker */
 214         gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
 215 }
 216
 217 int ft_board_setup(void *blob, bd_t *bd)
 218 {
 219         if (lvds_compat_string)
 220                 do_fixup_by_path_string(blob, "/panel", "compatible",
 221                                         lvds_compat_string);
 222
 223         return 0;
 224 }
 225
 226 struct display_info_t const displays[] = {
 227         {
 228                 .bus    = 0,
 229                 .addr   = 0,
 230                 .detect = detect_lvds,
 231                 .enable = enable_lvds_etm0430g0dh6,
 232                 .pixfmt = IPU_PIX_FMT_RGB666,
 233                 .mode   = {
 234                         .name           = "edt,etm0430g0dh6",
 235                         .refresh        = 60,
 236                         .xres           = 480,
 237                         .yres           = 272,
 238                         .pixclock       = 111111, /* picosecond (9 MHz) */
 239                         .left_margin    = 2,
 240                         .right_margin   = 2,
 241                         .upper_margin   = 2,
 242                         .lower_margin   = 2,
 243                         .hsync_len      = 41,
 244                         .vsync_len      = 10,
 245                         .sync           = 0x40000000,
 246                         .vmode          = FB_VMODE_NONINTERLACED
 247                 }
 248         }, {
 249                 .bus    = 0,
 250                 .addr   = 0,
 251                 .detect = detect_lvds,
 252                 .enable = enable_lvds_etm0700g0dh6,
 253                 .pixfmt = IPU_PIX_FMT_RGB666,
 254                 .mode   = {
 255                         .name           = "edt,etm0700g0dh6",
 256                         .refresh        = 60,
 257                         .xres           = 800,
 258                         .yres           = 480,
 259                         .pixclock       = 30048, /* picosecond (33.28 MHz) */
 260                         .left_margin    = 40,
 261                         .right_margin   = 88,
 262                         .upper_margin   = 10,
 263                         .lower_margin   = 33,
 264                         .hsync_len      = 128,
 265                         .vsync_len      = 2,
 266                         .sync           = FB_SYNC_EXT,
 267                         .vmode          = FB_VMODE_NONINTERLACED
 268                 }
 269         }
 270 };
 271
 272 size_t display_count = ARRAY_SIZE(displays);
 273 #endif
 274
 275 #ifdef CONFIG_SPLASH_SCREEN
 276 static struct splash_location default_splash_locations[] = {
 277         {
 278                 .name           = "mmc_fs",
 279                 .storage        = SPLASH_STORAGE_MMC,
 280                 .flags          = SPLASH_STORAGE_FS,
 281                 .devpart        = "0:1",
 282         },
 283 };
 284
 285 int splash_screen_prepare(void)
 286 {
 287         return splash_source_load(default_splash_locations,
 288                                   ARRAY_SIZE(default_splash_locations));
 289 }
 290 #endif
 291
 292 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 293                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 294
 295 static void setup_iomux_i2c(void)
 296 {
 297         static const iomux_v3_cfg_t i2c_pads[] = {
 298                 /* I2C1 */
 299                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
 300                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
 301                 /* I2C2 */
 302                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 303                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 304         };
 305
 306         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 307 }
 308
 309 static void setup_iomux_video(void)
 310 {
 311         static const iomux_v3_cfg_t lcd_pads[] = {
 312                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 313                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 314                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 315                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 316                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 317         };
 318
 319         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 320 }
 321
 322 static void setup_iomux_nand(void)
 323 {
 324         static const iomux_v3_cfg_t nand_pads[] = {
 325                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 326                              PAD_CTL_DSE_HIGH),
 327                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 328                              PAD_CTL_DSE_HIGH),
 329                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 330                              PAD_CTL_DSE_HIGH),
 331                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 332                              PAD_CTL_DSE_HIGH),
 333                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 334                              PAD_CTL_PUS_100K_UP),
 335                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 336                              PAD_CTL_PUS_100K_UP),
 337                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 338                              PAD_CTL_DSE_HIGH),
 339                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 340                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 341                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 342                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 343                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 344                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 345                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 346                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 347                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 348                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 349                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 350                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 351                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 352                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 353                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 354                              PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 355         };
 356
 357         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 358 }
 359
 360 static void m53_set_clock(void)
 361 {
 362         int ret;
 363         const u32 ref_clk = MXC_HCLK;
 364         const u32 dramclk = 400;
 365         u32 cpuclk;
 366
 367         gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
 368
 369         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 370                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 371         gpio_direction_input(IMX_GPIO_NR(4, 0));
 372
 373         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 374         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 375
 376         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 377         if (ret)
 378                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 379
 380         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 381         if (ret) {
 382                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 383                        dramclk);
 384         }
 385
 386         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 387         if (ret)
 388                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 389 }
 390
 391 static void m53_set_nand(void)
 392 {
 393         u32 i;
 394
 395         /* NAND flash is muxed on ATA pins */
 396         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 397
 398         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 399         for (i = 0x4; i < 0x94; i += 0x18) {
 400                 clrbits_le32(WEIM_BASE_ADDR + i,
 401                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 402         }
 403
 404         mxc_set_clock(0, 33, MXC_NFC_CLK);
 405         enable_nfc_clk(1);
 406 }
 407
 408 int board_early_init_f(void)
 409 {
 410         setup_iomux_uart();
 411         setup_iomux_fec();
 412         setup_iomux_i2c();
 413         setup_iomux_nand();
 414         setup_iomux_video();
 415
 416         m53_set_clock();
 417
 418         mxc_set_sata_internal_clock();
 419
 420         /* NAND clock @ 33MHz */
 421         m53_set_nand();
 422
 423         return 0;
 424 }
 425
 426 int board_init(void)
 427 {
 428         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 429
 430         return 0;
 431 }
 432
 433 int checkboard(void)
 434 {
 435         puts("Board: Menlosystems M53Menlo\n");
 436
 437         return 0;
 438 }
 439
 440 /*
 441  * NAND SPL
 442  */
 443 #ifdef CONFIG_SPL_BUILD
 444 void spl_board_init(void)
 445 {
 446         setup_iomux_nand();
 447         m53_set_clock();
 448         m53_set_nand();
 449 }
 450
 451 u32 spl_boot_device(void)
 452 {
 453         return BOOT_DEVICE_NAND;
 454 }
 455 #endif