2 * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
5 #define SDRAM_DDR 0 /* is SDR */
7 #if defined(CONFIG_MPC5200)
8 /* Settings for XLB = 132 MHz */
9 //#define SDRAM_MODE 0x00cc0000 // CL-3 BURST-8 -> Mode Register
\97MBAR + 0x0100
10 //#define SDRAM_CONTROL 0x501f0000 // Control Register
\97MBAR + 0x0104
11 //#define SDRAM_CONFIG1 0xe2329000 // Delays between commands -> Configuration Register 1
\97MBAR + 0x0108
12 //#define SDRAM_CONFIG2 0x46e70000 // Delays between commands -> Configuration Register 2
\97MBAR + 0x010C
15 //#define SDRAM_MODE 0x00cd0000 // CL-3 BURST-8 -> Mode Register
\97MBAR + 0x0100
16 //#define SDRAM_CONTROL 0x501f0000 // Control Register
\97MBAR + 0x0104
17 //#define SDRAM_CONFIG1 0xd2322900 // Delays between commands -> Configuration Register 1
\97MBAR + 0x0108
18 //#define SDRAM_CONFIG2 0x8ad70000 // Delays between commands -> Configuration Register 2
\97MBAR + 0x010C
20 //###CHD: ordentliche Doku dazu! CAS=2, etc.
22 #define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register
\97MBAR + 0x0100
23 #define SDRAM_CONTROL 0x504f0000 // Control Register
\97MBAR + 0x0104
24 #define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1
\97MBAR + 0x0108
25 #define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2
\97MBAR + 0x010C
29 #error CONFIG_MPC5200 not defined, please set parameters for your sdram controller in mt48lc8m32b2.h