2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 /* Two MT48LC8M32B2 for 32 MB */
33 /* #include "mt48lc8m32b2-6-7.h" */
35 /* One MT48LC16M32S2 for 64 MB */
36 /* #include "mt48lc16m32s2-75.h" */
37 #if defined (CONFIG_MCC200_SDRAM)
38 #include "mt48lc16m16a2-75.h"
40 #include "mt46v16m16-75.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 extern flash_info_t flash_info[]; /* FLASH chips info */
47 ulong flash_get_size (ulong base, int banknum);
50 static void sdram_start (int hi_addr)
52 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
54 /* unlock mode register */
55 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
56 __asm__ volatile ("sync");
58 /* precharge all banks */
59 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
60 __asm__ volatile ("sync");
63 /* set mode register: extended mode */
64 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
65 __asm__ volatile ("sync");
67 /* set mode register: reset DLL */
68 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
69 __asm__ volatile ("sync");
72 /* precharge all banks */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
74 __asm__ volatile ("sync");
77 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
78 __asm__ volatile ("sync");
80 /* set mode register */
81 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
82 __asm__ volatile ("sync");
84 /* normal operation */
85 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
86 __asm__ volatile ("sync");
93 * ATTENTION: Although partially referenced initdram does NOT make real use
94 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
95 * is something else than 0x00000000.
98 long int initdram (int board_type)
106 /* setup SDRAM chip selects */
107 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
108 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
109 __asm__ volatile ("sync");
111 /* setup config registers */
112 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
113 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
114 __asm__ volatile ("sync");
118 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
119 __asm__ volatile ("sync");
122 /* find RAM size using SDRAM CS0 only */
124 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
126 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
134 /* memory smaller than 1MB is impossible */
135 if (dramsize < (1 << 20)) {
139 /* set SDRAM CS0 size according to the amount of RAM found */
141 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
143 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
146 /* let SDRAM CS1 start right after CS0 */
147 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
149 /* find RAM size using SDRAM CS1 only */
152 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
155 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
164 /* memory smaller than 1MB is impossible */
165 if (dramsize2 < (1 << 20)) {
169 /* set SDRAM CS1 size according to the amount of RAM found */
171 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
172 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
174 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
177 #else /* CFG_RAMBOOT */
179 /* retrieve size of memory connected to SDRAM CS0 */
180 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
181 if (dramsize >= 0x13) {
182 dramsize = (1 << (dramsize - 0x13)) << 20;
187 /* retrieve size of memory connected to SDRAM CS1 */
188 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
189 if (dramsize2 >= 0x13) {
190 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
195 #endif /* CFG_RAMBOOT */
198 * On MPC5200B we need to set the special configuration delay in the
199 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
200 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
202 * "The SDelay should be written to a value of 0x00000004. It is
203 * required to account for changes caused by normal wafer processing
208 if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) &&
209 (PVR_MIN(pvr) == 4)) {
210 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
211 __asm__ volatile ("sync");
214 return dramsize + dramsize2;
217 int checkboard (void)
219 #if defined(CONFIG_PRS200)
220 puts ("Board: PRS200\n");
222 puts ("Board: MCC200\n");
227 int misc_init_r (void)
229 ulong flash_sup_end, snum;
232 * Adjust flash start and offset to detected values
234 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
235 gd->bd->bi_flashoffset = 0;
238 * Check if boot FLASH isn't max size
240 if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
242 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
243 START_REG(gd->bd->bi_flashstart);
244 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
245 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
248 * Re-check to get correct base address
250 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
253 * Re-do flash protection upon new addresses
255 flash_protect (FLAG_PROTECT_CLEAR,
256 gd->bd->bi_flashstart, 0xffffffff,
257 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
259 /* Monitor protection ON by default */
260 flash_protect (FLAG_PROTECT_SET,
261 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
262 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
264 /* Environment protection ON by default */
265 flash_protect (FLAG_PROTECT_SET,
267 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
268 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
270 /* Redundant environment protection ON by default */
271 flash_protect (FLAG_PROTECT_SET,
273 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
274 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
277 if (gd->bd->bi_flashsize > (32 << 20)) {
278 /* Unprotect the upper bank of the Flash */
279 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
280 flash_protect (FLAG_PROTECT_CLEAR,
281 flash_info[0].start[0] + flash_info[0].size / 2,
282 (flash_info[0].start[0] - 1) + flash_info[0].size,
284 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
285 printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
286 flash_info[0].size = 32 << 20;
287 for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
288 flash_info[0].start[snum] < flash_sup_end;
290 flash_info[0].sector_count = snum;
297 static struct pci_controller hose;
299 extern void pci_mpc5xxx_init(struct pci_controller *);
301 void pci_init_board(void)
303 pci_mpc5xxx_init(&hose);
307 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
309 void init_ide_reset (void)
311 debug ("init_ide_reset\n");
315 void ide_set_reset (int idereset)
317 debug ("ide_reset(%d)\n", idereset);
320 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
322 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
323 extern void doc_probe (ulong physadr);
326 doc_probe (CFG_DOC_BASE);