2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 //###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI!
32 #if defined(CONFIG_MPC5200_DDR)
33 #include "mt46v16m16-75.h"
35 //#include "mt48lc16m16a2-75.h"
36 #include "mt48lc8m32b2-6-7.h"
39 extern flash_info_t flash_info[]; /* FLASH chips info */
41 ulong flash_get_size (ulong base, int banknum);
43 //###CHD: wenn RAMBOOT gehen wuerde, ....
45 static void sdram_start (int hi_addr)
47 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
49 /* unlock mode register */
50 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
51 __asm__ volatile ("sync");
53 /* precharge all banks */
54 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
55 __asm__ volatile ("sync");
58 /* set mode register: extended mode */
59 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
60 __asm__ volatile ("sync");
62 /* set mode register: reset DLL */
63 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
64 __asm__ volatile ("sync");
67 /* precharge all banks */
68 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
69 __asm__ volatile ("sync");
72 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
73 __asm__ volatile ("sync");
75 /* set mode register */
76 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
77 __asm__ volatile ("sync");
79 /* normal operation */
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
81 __asm__ volatile ("sync");
86 * ATTENTION: Although partially referenced initdram does NOT make real use
87 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
88 * is something else than 0x00000000.
91 #if defined(CONFIG_MPC5200)
92 long int initdram (int board_type)
99 /* setup SDRAM chip selects */
100 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
101 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
102 __asm__ volatile ("sync");
104 /* setup config registers */
105 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
106 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
107 __asm__ volatile ("sync");
111 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
112 __asm__ volatile ("sync");
115 /* find RAM size using SDRAM CS0 only */
117 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
119 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
127 /* memory smaller than 1MB is impossible */
128 if (dramsize < (1 << 20)) {
132 /* set SDRAM CS0 size according to the amount of RAM found */
134 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
136 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
139 /* let SDRAM CS1 start right after CS0 */
140 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
142 /* find RAM size using SDRAM CS1 only */
145 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
148 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
157 /* memory smaller than 1MB is impossible */
158 if (dramsize2 < (1 << 20)) {
162 /* set SDRAM CS1 size according to the amount of RAM found */
164 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
165 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
167 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
170 #else /* CFG_RAMBOOT */
172 /* retrieve size of memory connected to SDRAM CS0 */
173 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
174 if (dramsize >= 0x13) {
175 dramsize = (1 << (dramsize - 0x13)) << 20;
180 /* retrieve size of memory connected to SDRAM CS1 */
181 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
182 if (dramsize2 >= 0x13) {
183 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
188 #endif /* CFG_RAMBOOT */
190 return dramsize + dramsize2;
193 //###CHD: sowas gibt es bei usn nicht!
194 #elif defined(CONFIG_MGT5100)
196 long int initdram (int board_type)
202 /* setup and enable SDRAM chip selects */
203 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
204 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
205 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
206 __asm__ volatile ("sync");
208 /* setup config registers */
209 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
210 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
212 /* address select register */
213 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
214 __asm__ volatile ("sync");
218 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
220 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
228 /* set SDRAM end address according to size */
229 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
231 #else /* CFG_RAMBOOT */
233 /* Retrieve amount of SDRAM available */
234 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
236 #endif /* CFG_RAMBOOT */
242 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
245 int checkboard (void)
247 puts ("Board: MCC200\n");
251 int misc_init_r (void)
253 DECLARE_GLOBAL_DATA_PTR;
256 * Adjust flash start and offset to detected values
258 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
259 gd->bd->bi_flashoffset = 0;
262 * Check if boot FLASH isn't max size
264 if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
266 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
267 START_REG(gd->bd->bi_flashstart);
268 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
269 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
272 * Re-check to get correct base address
274 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
277 * Re-do flash protection upon new addresses
279 flash_protect (FLAG_PROTECT_CLEAR,
280 gd->bd->bi_flashstart, 0xffffffff,
281 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
283 /* Monitor protection ON by default */
284 flash_protect (FLAG_PROTECT_SET,
285 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
286 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
288 /* Environment protection ON by default */
289 flash_protect (FLAG_PROTECT_SET,
291 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
292 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
294 /* Redundant environment protection ON by default */
295 flash_protect (FLAG_PROTECT_SET,
297 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
298 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
305 static struct pci_controller hose;
307 extern void pci_mpc5xxx_init(struct pci_controller *);
309 void pci_init_board(void)
311 pci_mpc5xxx_init(&hose);
315 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
317 void init_ide_reset (void)
319 debug ("init_ide_reset\n");
323 void ide_set_reset (int idereset)
325 debug ("ide_reset(%d)\n", idereset);
328 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
330 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
331 extern void doc_probe (ulong physadr);
334 doc_probe (CFG_DOC_BASE);