2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 /* Two MT48LC8M32B2 for 32 MB */
33 /* #include "mt48lc8m32b2-6-7.h" */
35 /* One MT48LC16M32S2 for 64 MB */
36 /* #include "mt48lc16m32s2-75.h" */
37 #if defined (CONFIG_MCC200_SDRAM)
38 #include "mt48lc16m16a2-75.h"
40 #include "mt46v16m16-75.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 extern flash_info_t flash_info[]; /* FLASH chips info */
47 extern int do_auto_update(void);
48 ulong flash_get_size (ulong base, int banknum);
50 #ifndef CONFIG_SYS_RAMBOOT
51 static void sdram_start (int hi_addr)
53 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
55 /* unlock mode register */
56 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
57 __asm__ volatile ("sync");
59 /* precharge all banks */
60 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
61 __asm__ volatile ("sync");
64 /* set mode register: extended mode */
65 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
66 __asm__ volatile ("sync");
68 /* set mode register: reset DLL */
69 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
70 __asm__ volatile ("sync");
73 /* precharge all banks */
74 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
75 __asm__ volatile ("sync");
78 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
79 __asm__ volatile ("sync");
81 /* set mode register */
82 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
83 __asm__ volatile ("sync");
85 /* normal operation */
86 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
87 __asm__ volatile ("sync");
94 * ATTENTION: Although partially referenced initdram does NOT make real use
95 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
96 * is something else than 0x00000000.
99 phys_size_t initdram (int board_type)
104 #ifndef CONFIG_SYS_RAMBOOT
107 /* setup SDRAM chip selects */
108 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
109 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
110 __asm__ volatile ("sync");
112 /* setup config registers */
113 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
114 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
115 __asm__ volatile ("sync");
119 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
120 __asm__ volatile ("sync");
123 /* find RAM size using SDRAM CS0 only */
125 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
127 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
135 /* memory smaller than 1MB is impossible */
136 if (dramsize < (1 << 20)) {
140 /* set SDRAM CS0 size according to the amount of RAM found */
142 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
144 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
147 /* let SDRAM CS1 start right after CS0 */
148 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
150 /* find RAM size using SDRAM CS1 only */
153 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
156 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
165 /* memory smaller than 1MB is impossible */
166 if (dramsize2 < (1 << 20)) {
170 /* set SDRAM CS1 size according to the amount of RAM found */
172 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
173 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
175 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
178 #else /* CONFIG_SYS_RAMBOOT */
180 /* retrieve size of memory connected to SDRAM CS0 */
181 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
182 if (dramsize >= 0x13) {
183 dramsize = (1 << (dramsize - 0x13)) << 20;
188 /* retrieve size of memory connected to SDRAM CS1 */
189 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
190 if (dramsize2 >= 0x13) {
191 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
196 #endif /* CONFIG_SYS_RAMBOOT */
199 * On MPC5200B we need to set the special configuration delay in the
200 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
201 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
203 * "The SDelay should be written to a value of 0x00000004. It is
204 * required to account for changes caused by normal wafer processing
209 if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
210 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
211 __asm__ volatile ("sync");
214 return dramsize + dramsize2;
217 int checkboard (void)
219 #if defined(CONFIG_PRS200)
220 puts ("Board: PRS200\n");
222 puts ("Board: MCC200\n");
227 int misc_init_r (void)
229 ulong flash_sup_end, snum;
232 * Adjust flash start and offset to detected values
234 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
235 gd->bd->bi_flashoffset = 0;
238 * Check if boot FLASH isn't max size
240 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
242 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
243 START_REG(gd->bd->bi_flashstart);
244 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
245 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
248 * Re-check to get correct base address
250 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
253 * Re-do flash protection upon new addresses
255 flash_protect (FLAG_PROTECT_CLEAR,
256 gd->bd->bi_flashstart, 0xffffffff,
257 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
259 /* Monitor protection ON by default */
260 flash_protect (FLAG_PROTECT_SET,
261 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
262 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
264 /* Environment protection ON by default */
265 flash_protect (FLAG_PROTECT_SET,
267 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
268 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
270 /* Redundant environment protection ON by default */
271 flash_protect (FLAG_PROTECT_SET,
272 CONFIG_ENV_ADDR_REDUND,
273 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
274 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
277 if (gd->bd->bi_flashsize > (32 << 20)) {
278 /* Unprotect the upper bank of the Flash */
279 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
280 flash_protect (FLAG_PROTECT_CLEAR,
281 flash_info[0].start[0] + flash_info[0].size / 2,
282 (flash_info[0].start[0] - 1) + flash_info[0].size,
284 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
285 printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
286 flash_info[0].size = 32 << 20;
287 for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
288 flash_info[0].start[snum] < flash_sup_end;
290 flash_info[0].sector_count = snum;
293 #ifdef CONFIG_AUTO_UPDATE
300 static struct pci_controller hose;
302 extern void pci_mpc5xxx_init(struct pci_controller *);
304 void pci_init_board(void)
306 pci_mpc5xxx_init(&hose);
310 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
312 void init_ide_reset (void)
314 debug ("init_ide_reset\n");
318 void ide_set_reset (int idereset)
320 debug ("ide_reset(%d)\n", idereset);
325 #if defined(CONFIG_CMD_DOC)
328 doc_probe (CONFIG_SYS_DOC_BASE);