2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <fdt_support.h>
38 #include <asm/processor.h>
41 #ifndef CONFIG_SYS_RAMBOOT
42 static void sdram_start (int hi_addr)
44 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
46 /* unlock mode register */
47 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
48 (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
49 __asm__ volatile ("sync");
51 /* precharge all banks */
52 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
53 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
54 __asm__ volatile ("sync");
57 /* set mode register: extended mode */
58 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
59 __asm__ volatile ("sync");
61 /* set mode register: reset DLL */
62 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
63 (SDRAM_MODE | 0x04000000));
64 __asm__ volatile ("sync");
67 /* precharge all banks */
68 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
69 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
70 __asm__ volatile ("sync");
73 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
74 (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
75 __asm__ volatile ("sync");
77 /* set mode register */
78 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
79 __asm__ volatile ("sync");
81 /* normal operation */
82 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
83 (SDRAM_CONTROL | hi_addr_bit));
84 __asm__ volatile ("sync");
89 * ATTENTION: Although partially referenced initdram does NOT make real use
90 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
91 * is something else than 0x00000000.
94 phys_size_t initdram (int board_type)
100 #ifndef CONFIG_SYS_RAMBOOT
103 /* setup SDRAM chip selects */
104 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
105 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
106 __asm__ volatile ("sync");
108 /* setup config registers */
109 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
110 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
111 __asm__ volatile ("sync");
115 out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
116 __asm__ volatile ("sync");
119 /* find RAM size using SDRAM CS0 only */
121 test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
123 test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
131 /* memory smaller than 1MB is impossible */
132 if (dramsize < (1 << 20)) {
136 /* set SDRAM CS0 size according to the amount of RAM found */
138 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
139 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
141 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
144 /* let SDRAM CS1 start right after CS0 */
145 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
147 /* find RAM size using SDRAM CS1 only */
150 test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
153 test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
162 /* memory smaller than 1MB is impossible */
163 if (dramsize2 < (1 << 20)) {
167 /* set SDRAM CS1 size according to the amount of RAM found */
169 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
170 (dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
172 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
175 #else /* CONFIG_SYS_RAMBOOT */
177 /* retrieve size of memory connected to SDRAM CS0 */
178 dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
179 if (dramsize >= 0x13) {
180 dramsize = (1 << (dramsize - 0x13)) << 20;
185 /* retrieve size of memory connected to SDRAM CS1 */
186 dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
187 if (dramsize2 >= 0x13) {
188 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
193 #endif /* CONFIG_SYS_RAMBOOT */
196 * On MPC5200B we need to set the special configuration delay in the
197 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
198 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
200 * "The SDelay should be written to a value of 0x00000004. It is
201 * required to account for changes caused by normal wafer processing
206 if ((SVR_MJREV(svr) >= 2) &&
207 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
209 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
210 __asm__ volatile ("sync");
213 return dramsize + dramsize2;
216 int checkboard (void)
218 puts ("Board: MUC.MC-52 HW WDT ");
219 #if defined(CONFIG_HW_WATCHDOG)
227 #ifdef CONFIG_PREBOOT
229 static uchar kbd_magic_prefix[] = "key_magic";
230 static uchar kbd_command_prefix[] = "key_cmd";
241 struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
243 kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
244 kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
249 static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
254 if (s1 >= '0' && s1 <= '9')
256 else if (s1 >= 'a' && s1 <= 'f')
258 else if (s1 >= 'A' && s1 <= 'F')
263 if (((S1_ROT & kbd_data->s1) >> 4) != s1)
266 s2 = (S2_Q | S2_M) & kbd_data->s2;
280 if (s2 == (S2_Q | S2_M))
292 static char *key_match (const struct kbd_data_t *kbd_data)
294 char magic[sizeof (kbd_magic_prefix) + 1];
296 char *kbd_magic_keys;
299 * The following string defines the characters that can be appended
300 * to "key_magic" to form the names of environment variables that
301 * hold "magic" key codes, i. e. such key codes that can cause
302 * pre-boot actions. If the string is empty (""), then only
303 * "key_magic" is checked (old behaviour); the string "125" causes
304 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
306 if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
309 /* loop over all magic keys;
310 * use '\0' suffix in case of empty string
312 for (suffix = kbd_magic_keys; *suffix ||
313 suffix == kbd_magic_keys; ++suffix) {
314 sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
316 if (compare_magic(kbd_data, getenv(magic)) == 0) {
317 char cmd_name[sizeof (kbd_command_prefix) + 1];
320 sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
321 cmd = getenv (cmd_name);
330 #endif /* CONFIG_PREBOOT */
332 int misc_init_r (void)
334 #ifdef CONFIG_PREBOOT
335 struct kbd_data_t kbd_data;
337 char *str = strdup (key_match (get_keys (&kbd_data)));
338 /* Set or delete definition */
339 setenv ("preboot", str);
341 #endif /* CONFIG_PREBOOT */
343 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
344 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
345 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
346 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
347 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
348 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
349 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
350 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
355 int board_early_init_r (void)
357 out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
358 out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
359 out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
360 out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
361 STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
362 out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
363 STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
367 int last_stage_init (void)
369 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
370 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
371 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
372 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
373 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
374 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
375 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
376 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
381 #if defined(CONFIG_HW_WATCHDOG)
382 #define GPT_OUT_0 0x00000027
383 #define GPT_OUT_1 0x00000037
384 void hw_watchdog_reset (void)
386 /* Trigger HW Watchdog with TIMER_0 */
387 out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
388 out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
393 static struct pci_controller hose;
395 extern void pci_mpc5xxx_init (struct pci_controller *);
397 void pci_init_board (void)
399 pci_mpc5xxx_init (&hose);
403 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
404 void ft_board_setup(void *blob, bd_t *bd)
406 ft_cpu_setup(blob, bd);
408 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */