2 * (C) Copyright 2003-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/processor.h>
20 #ifndef CONFIG_SYS_RAMBOOT
21 static void sdram_start (int hi_addr)
23 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
25 /* unlock mode register */
26 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
27 __asm__ volatile ("sync");
29 /* precharge all banks */
30 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
31 __asm__ volatile ("sync");
34 /* set mode register: extended mode */
35 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
36 __asm__ volatile ("sync");
38 /* set mode register: reset DLL */
39 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
40 __asm__ volatile ("sync");
43 /* precharge all banks */
44 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
45 __asm__ volatile ("sync");
48 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
49 __asm__ volatile ("sync");
51 /* set mode register */
52 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
53 __asm__ volatile ("sync");
55 /* normal operation */
56 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
57 __asm__ volatile ("sync");
62 * ATTENTION: Although partially referenced initdram does NOT make real use
63 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
64 * is something else than 0x00000000.
67 phys_size_t initdram (int board_type)
70 #ifndef CONFIG_SYS_RAMBOOT
74 /* setup SDRAM chip selects */
75 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
76 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
77 __asm__ volatile ("sync");
79 /* setup config registers */
80 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
81 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
82 __asm__ volatile ("sync");
86 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
87 __asm__ volatile ("sync");
90 /* find RAM size using SDRAM CS0 only */
92 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
94 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
102 /* memory smaller than 1MB is impossible */
103 if (dramsize < (1 << 20)) {
107 /* set SDRAM CS0 size according to the amount of RAM found */
109 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
110 __builtin_ffs(dramsize >> 20) - 1;
112 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
115 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
116 #else /* CONFIG_SYS_RAMBOOT */
118 /* retrieve size of memory connected to SDRAM CS0 */
119 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
120 if (dramsize >= 0x13) {
121 dramsize = (1 << (dramsize - 0x13)) << 20;
126 /* retrieve size of memory connected to SDRAM CS1 */
127 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
128 if (dramsize2 >= 0x13) {
129 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
134 #endif /* CONFIG_SYS_RAMBOOT */
137 * On MPC5200B we need to set the special configuration delay in the
138 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
139 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
141 * "The SDelay should be written to a value of 0x00000004. It is
142 * required to account for changes caused by normal wafer processing
147 if ((SVR_MJREV(svr) >= 2) &&
148 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
150 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
151 __asm__ volatile ("sync");
154 /* return dramsize + dramsize2; */
158 int checkboard (void)
160 puts ("Board: HMI1001\n");
164 #ifdef CONFIG_PREBOOT
166 static uchar kbd_magic_prefix[] = "key_magic";
167 static uchar kbd_command_prefix[] = "key_cmd";
178 struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
180 kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE));
181 kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE));
186 static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
191 if (s1 >= '0' && s1 <= '9')
193 else if (s1 >= 'a' && s1 <= 'f')
195 else if (s1 >= 'A' && s1 <= 'F')
200 if (((S1_ROT & kbd_data->s1) >> 4) != s1)
203 s2 = (S2_Q | S2_M) & kbd_data->s2;
217 if (s2 == (S2_Q | S2_M))
229 static char *key_match (const struct kbd_data_t *kbd_data)
231 char magic[sizeof (kbd_magic_prefix) + 1];
233 char *kbd_magic_keys;
236 * The following string defines the characters that can be appended
237 * to "key_magic" to form the names of environment variables that
238 * hold "magic" key codes, i. e. such key codes that can cause
239 * pre-boot actions. If the string is empty (""), then only
240 * "key_magic" is checked (old behaviour); the string "125" causes
241 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
243 if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
246 /* loop over all magic keys;
247 * use '\0' suffix in case of empty string
249 for (suffix = kbd_magic_keys; *suffix ||
250 suffix == kbd_magic_keys; ++suffix) {
251 sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
253 if (compare_magic(kbd_data, getenv(magic)) == 0) {
254 char cmd_name[sizeof (kbd_command_prefix) + 1];
257 sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
258 cmd = getenv (cmd_name);
267 #endif /* CONFIG_PREBOOT */
269 int misc_init_r (void)
271 #ifdef CONFIG_PREBOOT
272 struct kbd_data_t kbd_data;
274 char *str = strdup (key_match (get_keys (&kbd_data)));
275 /* Set or delete definition */
276 setenv ("preboot", str);
278 #endif /* CONFIG_PREBOOT */
283 int board_early_init_r (void)
285 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
286 *(vu_long *)MPC5XXX_BOOTCS_START =
287 *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
288 *(vu_long *)MPC5XXX_BOOTCS_STOP =
289 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
293 static struct pci_controller hose;
295 extern void pci_mpc5xxx_init(struct pci_controller *);
297 void pci_init_board(void)
299 pci_mpc5xxx_init(&hose);