2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the at91rm9200dk board by
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #ifdef CONFIG_BOOTBINFUNC
35 * some parameters for the board
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
38 * turn is based on the boot.bin code from ATMEL
43 #define MC_PUIA 0xFFFFFF10
44 #define MC_PUIA_VAL 0x00000000
45 #define MC_PUP 0xFFFFFF50
46 #define MC_PUP_VAL 0x00000000
47 #define MC_PUER 0xFFFFFF54
48 #define MC_PUER_VAL 0x00000000
49 #define MC_ASR 0xFFFFFF04
50 #define MC_ASR_VAL 0x00000000
51 #define MC_AASR 0xFFFFFF08
52 #define MC_AASR_VAL 0x00000000
53 #define EBI_CFGR 0xFFFFFF64
54 #define EBI_CFGR_VAL 0x00000000
55 #define SMC_CSR0 0xFFFFFF70
56 #define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
59 #define PLLAR 0xFFFFFC28
60 #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
61 #define PLLBR 0xFFFFFC2C
62 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
63 #define MCKR 0xFFFFFC30
64 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
65 #define MCKR_VAL 0x00000202
68 #define PIOC_ASR 0xFFFFF870
69 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
70 #define PIOC_BSR 0xFFFFF874
71 #define PIOC_BSR_VAL 0x00000000
72 #define PIOC_PDR 0xFFFFF804
73 #define PIOC_PDR_VAL 0xFFFF0000
74 #define EBI_CSA 0xFFFFFF60
75 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
76 #define SDRC_CR 0xFFFFFF98
77 #define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
78 #define SDRAM 0x20000000 /* address of the SDRAM */
79 #define SDRAM1 0x20000080 /* address of the SDRAM */
80 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */
81 #define SDRC_MR 0xFFFFFF90
82 #define SDRC_MR_VAL 0x00000002 /* Precharge All */
83 #define SDRC_MR_VAL1 0x00000004 /* refresh */
84 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
85 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
86 #define SDRC_TR 0xFFFFFF94
87 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
94 /* memory control configuration */
95 /* this isn't very elegant, but what the heck */
108 /* delay - this is all done by guess */
126 /* everything is fine now */
152 /* SMRDATA is 80 bytes long */
153 /* here there's a delay of 100 */
199 /* SMRDATA1 is 176 bytes long */
200 #endif /* CONFIG_BOOTBINFUNC */