3 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
5 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
9 * (C) Copyright 2007-2008
10 * Stefan Roese, DENX Software Engineering, sr@denx.de.
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* define DEBUG for debugging output (obviously ;-)) */
34 #include <asm/processor.h>
41 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
42 * region. Right now the cache should still be disabled in U-Boot because of the
43 * EMAC driver, that need it's buffer descriptor to be located in non cached
46 * If at some time this restriction doesn't apply anymore, just define
47 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
48 * everything correctly.
50 #ifdef CFG_ENABLE_SDRAM_CACHE
51 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
53 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
56 /*-----------------------------------------------------------------------------+
58 *-----------------------------------------------------------------------------*/
59 extern int denali_wait_for_dlllock(void);
60 extern void denali_core_search_data_eye(void);
61 extern void dcbz_area(u32 start_address, u32 num_bytes);
62 extern void dflush(void);
64 static u32 is_ecc_enabled(void)
68 mfsdram(DDR0_22, val);
69 val &= DDR0_22_CTRL_RAW_MASK;
76 void board_add_ram_info(int use_default)
78 PPC4xx_SYS_INFO board_cfg;
86 get_sys_info(&board_cfg);
87 printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
89 mfsdram(DDR0_03, val);
90 val = DDR0_03_CASLAT_DECODE(val);
91 printf(", CL%d)", val);
95 static void wait_ddr_idle(void)
98 * Controller idle status cannot be determined for Denali
99 * DDR2 code. Just return here.
103 static void program_ecc(u32 start_address,
105 u32 tlb_word2_i_value)
108 u32 current_addr = start_address;
115 * Because of 440EPx errata CHIP 11, we don't touch the last 256
118 bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
121 * We have to write the ECC bytes by zeroing and flushing in smaller
122 * steps, since the whole 256MByte takes too long for the external
125 while (bytes_remaining > 0) {
126 dcbz_area(current_addr, min((64 << 20), bytes_remaining));
127 current_addr += 64 << 20;
128 bytes_remaining -= 64 << 20;
136 /* Clear error status */
137 mfsdram(DDR0_00, val);
138 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
140 /* Set 'int_mask' parameter to functionnal value */
141 mfsdram(DDR0_01, val);
142 mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
149 /*************************************************************************
151 * initdram -- 440EPx's DDR controller is a DENALI Core
153 ************************************************************************/
154 long int initdram (int board_type)
156 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
158 mtsdram(DDR0_02, 0x00000000);
160 mtsdram(DDR0_00, 0x0000190A);
161 mtsdram(DDR0_01, 0x01000000);
162 mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
164 mtsdram(DDR0_04, 0x0A030300);
165 mtsdram(DDR0_05, 0x02020308);
166 mtsdram(DDR0_06, 0x0103C812);
167 mtsdram(DDR0_07, 0x00090100);
168 mtsdram(DDR0_08, 0x02c80001);
169 mtsdram(DDR0_09, 0x00011D5F);
170 mtsdram(DDR0_10, 0x00000300);
171 mtsdram(DDR0_11, 0x000CC800);
172 mtsdram(DDR0_12, 0x00000003);
173 mtsdram(DDR0_14, 0x00000000);
174 mtsdram(DDR0_17, 0x1e000000);
175 mtsdram(DDR0_18, 0x1e1e1e1e);
176 mtsdram(DDR0_19, 0x1e1e1e1e);
177 mtsdram(DDR0_20, 0x0B0B0B0B);
178 mtsdram(DDR0_21, 0x0B0B0B0B);
179 #ifdef CONFIG_DDR_ECC
180 mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
182 mtsdram(DDR0_22, 0x00267F0B);
185 mtsdram(DDR0_23, 0x01000000);
186 mtsdram(DDR0_24, 0x01010001);
188 mtsdram(DDR0_26, 0x2D93028A);
189 mtsdram(DDR0_27, 0x0784682B);
191 mtsdram(DDR0_28, 0x00000080);
192 mtsdram(DDR0_31, 0x00000000);
193 mtsdram(DDR0_42, 0x01000006);
195 mtsdram(DDR0_43, 0x030A0200);
196 mtsdram(DDR0_44, 0x00000003);
197 mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
200 mtsdram(DDR0_02, 0x00000000);
202 mtsdram(DDR0_00, 0x0000190A);
203 mtsdram(DDR0_01, 0x01000000);
204 mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
206 mtsdram(DDR0_04, 0x0B030300);
207 mtsdram(DDR0_05, 0x02020308);
208 mtsdram(DDR0_06, 0x0003C812);
209 mtsdram(DDR0_07, 0x00090100);
210 mtsdram(DDR0_08, 0x03c80001);
211 mtsdram(DDR0_09, 0x00011D5F);
212 mtsdram(DDR0_10, 0x00000300);
213 mtsdram(DDR0_11, 0x000CC800);
214 mtsdram(DDR0_12, 0x00000003);
215 mtsdram(DDR0_14, 0x00000000);
216 mtsdram(DDR0_17, 0x1e000000);
217 mtsdram(DDR0_18, 0x1e1e1e1e);
218 mtsdram(DDR0_19, 0x1e1e1e1e);
219 mtsdram(DDR0_20, 0x0B0B0B0B);
220 mtsdram(DDR0_21, 0x0B0B0B0B);
221 #ifdef CONFIG_DDR_ECC
222 mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
224 mtsdram(DDR0_22, 0x00267F0B);
227 mtsdram(DDR0_23, 0x01000000);
228 mtsdram(DDR0_24, 0x01010001);
230 mtsdram(DDR0_26, 0x2D93028A);
231 mtsdram(DDR0_27, 0x0784682B);
233 mtsdram(DDR0_28, 0x00000080);
234 mtsdram(DDR0_31, 0x00000000);
235 mtsdram(DDR0_42, 0x01000008);
237 mtsdram(DDR0_43, 0x050A0200);
238 mtsdram(DDR0_44, 0x00000005);
239 mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
242 denali_wait_for_dlllock();
244 #if defined(CONFIG_DDR_DATA_EYE)
245 /* -----------------------------------------------------------+
246 * Perform data eye search if requested.
247 * ----------------------------------------------------------*/
248 program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
250 denali_core_search_data_eye();
251 remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
255 * Program tlb entries for this size (dynamic)
257 program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
258 MY_TLB_WORD2_I_ENABLE);
261 * Setup 2nd TLB with same physical address but different virtual address
262 * with cache enabled. This is done for fast ECC generation.
264 program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
266 #ifdef CONFIG_DDR_ECC
268 * If ECC is enabled, initialize the parity bits.
270 program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
274 * Clear possible errors resulting from data-eye-search.
275 * If not done, then we could get an interrupt later on when
276 * exceptions are enabled.
278 set_mcsr(get_mcsr());
280 return (CFG_MBYTES_SDRAM << 20);