3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/processor.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
31 ulong flash_get_size(ulong base, int banknum);
32 int misc_init_r_kbd(void);
34 int board_early_init_f(void)
36 u32 sdr0_pfc1, sdr0_pfc2;
39 /* PLB Write pipelining disabled. Denali Core workaround */
40 mtdcr(plb0_acr, 0xDE000000);
41 mtdcr(plb1_acr, 0xDE000000);
43 /*--------------------------------------------------------------------
44 * Setup the interrupt controller polarities, triggers, etc.
45 *-------------------------------------------------------------------*/
46 mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
47 mtdcr(uic0er, 0x00000000); /* disable all */
48 mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
49 mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
50 mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
51 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
52 mtdcr(uic0sr, 0xffffffff); /* clear all */
54 mtdcr(uic1sr, 0xffffffff); /* clear all */
55 mtdcr(uic1er, 0x00000000); /* disable all */
56 mtdcr(uic1cr, 0x00000000); /* all non-critical */
57 mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
58 mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
59 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
60 mtdcr(uic1sr, 0xffffffff); /* clear all */
62 mtdcr(uic2sr, 0xffffffff); /* clear all */
63 mtdcr(uic2er, 0x00000000); /* disable all */
64 mtdcr(uic2cr, 0x00000000); /* all non-critical */
65 mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
66 mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
67 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
68 mtdcr(uic2sr, 0xffffffff); /* clear all */
70 /* Trace Pins are disabled. SDR0_PFC0 Register */
71 mtsdr(SDR0_PFC0, 0x0);
73 /* select Ethernet pins */
74 mfsdr(SDR0_PFC1, sdr0_pfc1);
76 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
77 SDR0_PFC1_SELECT_CONFIG_6;
78 mfsdr(SDR0_PFC2, sdr0_pfc2);
79 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
80 SDR0_PFC2_SELECT_CONFIG_6;
82 /* enable SPI (SCP) */
83 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
85 mtsdr(SDR0_PFC2, sdr0_pfc2);
86 mtsdr(SDR0_PFC1, sdr0_pfc1);
88 mtsdr(SDR0_PFC4, 0x80000000);
90 /* PCI arbiter disabled */
91 /* PCI Host Configuration disbaled */
94 mtsdr(sdr_pci0, 0x00000000 | reg);
96 gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
101 /*---------------------------------------------------------------------------+
103 +---------------------------------------------------------------------------*/
104 int misc_init_r(void)
109 unsigned long usb2d0cr = 0;
110 unsigned long usb2phy0cr, usb2h0cr = 0;
111 unsigned long sdr0_pfc1;
117 /* Re-do sizing to get full correct info */
119 /* adjust flash start and offset */
120 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
121 gd->bd->bi_flashoffset = 0;
124 switch (gd->bd->bi_flashsize) {
150 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
154 * Re-check to get correct base address
156 flash_get_size(gd->bd->bi_flashstart, 0);
158 /* Monitor protection ON by default */
159 (void)flash_protect(FLAG_PROTECT_SET,
164 /* Env protection ON by default */
165 (void)flash_protect(FLAG_PROTECT_SET,
167 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
174 mfsdr(SDR0_PFC1, sdr0_pfc1);
175 mfsdr(SDR0_USB0, usb2d0cr);
176 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
177 mfsdr(SDR0_USB2H0CR, usb2h0cr);
179 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
180 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
181 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
182 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
183 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
184 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
185 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
186 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
187 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
188 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
190 /* An 8-bit/60MHz interface is the only possible alternative
191 when connecting the Device to the PHY */
192 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
193 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
195 mtsdr(SDR0_PFC1, sdr0_pfc1);
196 mtsdr(SDR0_USB0, usb2d0cr);
197 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
198 mtsdr(SDR0_USB2H0CR, usb2h0cr);
204 mtsdr(SDR0_SRST1, 0x00000000);
206 mtsdr(SDR0_SRST0, 0x00000000);
208 printf("USB: Host(int phy) Device(ext phy)\n");
211 * Clear PLB4A0_ACR[WRP]
212 * This fix will make the MAL burst disabling patch for the Linux
213 * EMAC driver obsolete.
215 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
216 mtdcr(plb4_acr, reg);
219 * Reset Lime controller
221 gpio_write_bit(CFG_GPIO_LIME_S, 1);
223 gpio_write_bit(CFG_GPIO_LIME_RST, 1);
225 /* Lime memory clock adjusted to 100MHz */
226 out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
227 /* Wait untill time expired. Because of requirements in lime manual */
229 /* Write lime controller memory parameters */
230 out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
235 gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
236 gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
238 gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
239 gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
242 * Init display controller
244 /* Setup dot clock (internal PLL, division rate 1/16) */
245 out_be32((void *)0xc1fd0100, 0x00000f00);
247 /* Lime L0 init (16 bpp, 640x480) */
248 out_be32((void *)0xc1fd0020, 0x801401df);
249 out_be32((void *)0xc1fd0024, 0x0);
250 out_be32((void *)0xc1fd0028, 0x0);
251 out_be32((void *)0xc1fd002c, 0x0);
252 out_be32((void *)0xc1fd0110, 0x0);
253 out_be32((void *)0xc1fd0114, 0x0);
254 out_be32((void *)0xc1fd0118, 0x01df0280);
256 /* Display timing init */
257 out_be32((void *)0xc1fd0004, 0x031f0000);
258 out_be32((void *)0xc1fd0008, 0x027f027f);
259 out_be32((void *)0xc1fd000c, 0x015f028f);
260 out_be32((void *)0xc1fd0010, 0x020c0000);
261 out_be32((void *)0xc1fd0014, 0x01df01ea);
262 out_be32((void *)0xc1fd0018, 0x0);
263 out_be32((void *)0xc1fd001c, 0x01e00280);
267 * Clear framebuffer using Lime's drawing engine
268 * (draw blue rect. with white border around it)
270 /* Setup mode and fbbase, xres, fg, bg */
271 out_be32((void *)0xc1ff0420, 0x8300);
272 out_be32((void *)0xc1ff0440, 0x0000);
273 out_be32((void *)0xc1ff0444, 0x0280);
274 out_be32((void *)0xc1ff0480, 0x7fff);
275 out_be32((void *)0xc1ff0484, 0x0000);
276 /* Reset clipping rectangle */
277 out_be32((void *)0xc1ff0454, 0x0000);
278 out_be32((void *)0xc1ff0458, 0x0280);
279 out_be32((void *)0xc1ff045c, 0x0000);
280 out_be32((void *)0xc1ff0460, 0x01e0);
281 /* Draw white rect. */
282 out_be32((void *)0xc1ff04a0, 0x09410000);
283 out_be32((void *)0xc1ff04a0, 0x00000000);
284 out_be32((void *)0xc1ff04a0, 0x01e00280);
286 /* Draw blue rect. */
287 out_be32((void *)0xc1ff0480, 0x001f);
288 out_be32((void *)0xc1ff04a0, 0x09410000);
289 out_be32((void *)0xc1ff04a0, 0x00010001);
290 out_be32((void *)0xc1ff04a0, 0x01de027e);
292 /* Display enable, L0 layer */
293 out_be32((void *)0xc1fd0100, 0x80010f00);
295 /* TFT-LCD enable - PWM duty, lamp on */
296 out_be32((void *)0xc4000024, 0x64);
297 out_be32((void *)0xc4000020, 0x701);
300 * Init matrix keyboard
309 char *s = getenv("serial#");
311 printf("Board: lwmon5");
322 #if defined(CFG_DRAM_TEST)
325 unsigned long *mem = (unsigned long *)0;
326 const unsigned long kend = (1024 / sizeof(unsigned long));
331 for (k = 0; k < CFG_MBYTES_SDRAM;
332 ++k, mem += (1024 / sizeof(unsigned long))) {
333 if ((k & 1023) == 0) {
334 printf("%3d MB\r", k / 1024);
337 memset(mem, 0xaaaaaaaa, 1024);
338 for (n = 0; n < kend; ++n) {
339 if (mem[n] != 0xaaaaaaaa) {
340 printf("SDRAM test fails at: %08x\n",
346 memset(mem, 0x55555555, 1024);
347 for (n = 0; n < kend; ++n) {
348 if (mem[n] != 0x55555555) {
349 printf("SDRAM test fails at: %08x\n",
355 printf("SDRAM test passes\n");
360 /*************************************************************************
363 * This routine is called just prior to registering the hose and gives
364 * the board the opportunity to check things. Returning a value of zero
365 * indicates that things are bad & PCI initialization should be aborted.
367 * Different boards may wish to customize the pci controller structure
368 * (add regions, override default access routines, etc) or perform
369 * certain pre-initialization actions.
371 ************************************************************************/
372 #if defined(CONFIG_PCI)
373 int pci_pre_init(struct pci_controller *hose)
377 /*-------------------------------------------------------------------------+
378 | Set priority for all PLB3 devices to 0.
379 | Set PLB3 arbiter to fair mode.
380 +-------------------------------------------------------------------------*/
381 mfsdr(sdr_amp1, addr);
382 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
383 addr = mfdcr(plb3_acr);
384 mtdcr(plb3_acr, addr | 0x80000000);
386 /*-------------------------------------------------------------------------+
387 | Set priority for all PLB4 devices to 0.
388 +-------------------------------------------------------------------------*/
389 mfsdr(sdr_amp0, addr);
390 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
391 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
392 mtdcr(plb4_acr, addr);
394 /*-------------------------------------------------------------------------+
395 | Set Nebula PLB4 arbiter to fair mode.
396 +-------------------------------------------------------------------------*/
398 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
399 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
400 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
401 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
402 mtdcr(plb0_acr, addr);
405 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
406 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
407 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
408 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
409 mtdcr(plb1_acr, addr);
413 #endif /* defined(CONFIG_PCI) */
415 /*************************************************************************
418 * The bootstrap configuration provides default settings for the pci
419 * inbound map (PIM). But the bootstrap config choices are limited and
420 * may not be sufficient for a given board.
422 ************************************************************************/
423 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
424 void pci_target_init(struct pci_controller *hose)
426 /*--------------------------------------------------------------------------+
427 * Set up Direct MMIO registers
428 *--------------------------------------------------------------------------*/
429 /*--------------------------------------------------------------------------+
430 | PowerPC440EPX PCI Master configuration.
431 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
432 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
433 | Use byte reversed out routines to handle endianess.
434 | Make this region non-prefetchable.
435 +--------------------------------------------------------------------------*/
436 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
437 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
438 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
439 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
440 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
442 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
443 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
444 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
445 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
446 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
448 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
449 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
450 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
451 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
453 /*--------------------------------------------------------------------------+
454 * Set up Configuration registers
455 *--------------------------------------------------------------------------*/
457 /* Program the board's subsystem id/vendor id */
458 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
459 CFG_PCI_SUBSYS_VENDORID);
460 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
462 /* Configure command register as bus master */
463 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
465 /* 240nS PCI clock */
466 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
468 /* No error reporting */
469 pci_write_config_word(0, PCI_ERREN, 0);
471 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
474 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
476 /*************************************************************************
479 ************************************************************************/
480 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
481 void pci_master_init(struct pci_controller *hose)
483 unsigned short temp_short;
485 /*--------------------------------------------------------------------------+
486 | Write the PowerPC440 EP PCI Configuration regs.
487 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
488 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
489 +--------------------------------------------------------------------------*/
490 pci_read_config_word(0, PCI_COMMAND, &temp_short);
491 pci_write_config_word(0, PCI_COMMAND,
492 temp_short | PCI_COMMAND_MASTER |
495 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
497 /*************************************************************************
500 * This routine is called to determine if a pci scan should be
501 * performed. With various hardware environments (especially cPCI and
502 * PPMC) it's insufficient to depend on the state of the arbiter enable
503 * bit in the strap register, or generic host/adapter assumptions.
505 * Rather than hard-code a bad assumption in the general 440 code, the
506 * 440 pci code requires the board to decide at runtime.
508 * Return 0 for adapter mode, non-zero for host (monarch) mode.
511 ************************************************************************/
512 #if defined(CONFIG_PCI)
513 int is_pci_host(struct pci_controller *hose)
515 /* Cactus is always configured as host. */
518 #endif /* defined(CONFIG_PCI) */
520 void hw_watchdog_reset(void)
525 * Toggle watchdog output
527 val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
528 gpio_write_bit(CFG_GPIO_WATCHDOG, val);