3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/processor.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
31 ulong flash_get_size (ulong base, int banknum);
33 int board_early_init_f(void)
35 u32 sdr0_pfc1, sdr0_pfc2;
38 /* PLB Write pipelining disabled. Denali Core workaround */
39 mtdcr(plb0_acr, 0xDE000000);
40 mtdcr(plb1_acr, 0xDE000000);
42 /*--------------------------------------------------------------------
43 * Setup the interrupt controller polarities, triggers, etc.
44 *-------------------------------------------------------------------*/
45 mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
46 mtdcr(uic0er, 0x00000000); /* disable all */
47 mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
48 mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
49 mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
50 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
51 mtdcr(uic0sr, 0xffffffff); /* clear all */
53 mtdcr(uic1sr, 0xffffffff); /* clear all */
54 mtdcr(uic1er, 0x00000000); /* disable all */
55 mtdcr(uic1cr, 0x00000000); /* all non-critical */
56 mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
57 mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
58 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
59 mtdcr(uic1sr, 0xffffffff); /* clear all */
61 mtdcr(uic2sr, 0xffffffff); /* clear all */
62 mtdcr(uic2er, 0x00000000); /* disable all */
63 mtdcr(uic2cr, 0x00000000); /* all non-critical */
64 mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
65 mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
66 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
67 mtdcr(uic2sr, 0xffffffff); /* clear all */
69 /* Trace Pins are disabled. SDR0_PFC0 Register */
70 mtsdr(SDR0_PFC0, 0x0);
72 /* select Ethernet pins */
73 mfsdr(SDR0_PFC1, sdr0_pfc1);
75 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
76 SDR0_PFC1_SELECT_CONFIG_6;
77 mfsdr(SDR0_PFC2, sdr0_pfc2);
78 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
79 SDR0_PFC2_SELECT_CONFIG_6;
81 /* enable SPI (SCP) */
82 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
84 mtsdr(SDR0_PFC2, sdr0_pfc2);
85 mtsdr(SDR0_PFC1, sdr0_pfc1);
87 mtsdr(SDR0_PFC4, 0x80000000);
89 /* PCI arbiter disabled */
90 /* PCI Host Configuration disbaled */
93 mtsdr(sdr_pci0, 0x00000000 | reg);
95 gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
100 /*---------------------------------------------------------------------------+
102 +---------------------------------------------------------------------------*/
103 int misc_init_r(void)
108 unsigned long usb2d0cr = 0;
109 unsigned long usb2phy0cr, usb2h0cr = 0;
110 unsigned long sdr0_pfc1;
116 /* Re-do sizing to get full correct info */
118 /* adjust flash start and offset */
119 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
120 gd->bd->bi_flashoffset = 0;
123 switch (gd->bd->bi_flashsize) {
149 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
153 * Re-check to get correct base address
155 flash_get_size(gd->bd->bi_flashstart, 0);
157 /* Monitor protection ON by default */
158 (void)flash_protect(FLAG_PROTECT_SET,
163 /* Env protection ON by default */
164 (void)flash_protect(FLAG_PROTECT_SET,
166 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
173 mfsdr(SDR0_PFC1, sdr0_pfc1);
174 mfsdr(SDR0_USB0, usb2d0cr);
175 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
176 mfsdr(SDR0_USB2H0CR, usb2h0cr);
178 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
179 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
180 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
181 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
182 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
183 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
184 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
185 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
186 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
187 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
189 /* An 8-bit/60MHz interface is the only possible alternative
190 when connecting the Device to the PHY */
191 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
192 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
194 mtsdr(SDR0_PFC1, sdr0_pfc1);
195 mtsdr(SDR0_USB0, usb2d0cr);
196 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
197 mtsdr(SDR0_USB2H0CR, usb2h0cr);
203 mtsdr(SDR0_SRST1, 0x00000000);
205 mtsdr(SDR0_SRST0, 0x00000000);
207 printf("USB: Host(int phy) Device(ext phy)\n");
210 * Clear PLB4A0_ACR[WRP]
211 * This fix will make the MAL burst disabling patch for the Linux
212 * EMAC driver obsolete.
214 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
215 mtdcr(plb4_acr, reg);
218 * Reset Lime controller
220 gpio_write_bit(CFG_GPIO_LIME_S, 1);
222 gpio_write_bit(CFG_GPIO_LIME_RST, 1);
224 /* Lime memory clock adjusted to 100MHz */
225 out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
226 /* Wait untill time expired. Because of requirements in lime manual */
228 /* Write lime controller memory parameters */
229 out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
234 gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
235 gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
237 gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
238 gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
241 * Init display controller
243 /* Setup dot clock (internal PLL, division rate 1/16) */
244 out_be32((void *)0xc1fd0100, 0x00000f00);
246 /* Lime L0 init (16 bpp, 640x480) */
247 out_be32((void *)0xc1fd0020, 0x801401df);
248 out_be32((void *)0xc1fd0024, 0x0);
249 out_be32((void *)0xc1fd0028, 0x0);
250 out_be32((void *)0xc1fd002c, 0x0);
251 out_be32((void *)0xc1fd0110, 0x0);
252 out_be32((void *)0xc1fd0114, 0x0);
253 out_be32((void *)0xc1fd0118, 0x01df0280);
255 /* Display timing init */
256 out_be32((void *)0xc1fd0004, 0x031f0000);
257 out_be32((void *)0xc1fd0008, 0x027f027f);
258 out_be32((void *)0xc1fd000c, 0x015f028f);
259 out_be32((void *)0xc1fd0010, 0x020c0000);
260 out_be32((void *)0xc1fd0014, 0x01df01ea);
261 out_be32((void *)0xc1fd0018, 0x0);
262 out_be32((void *)0xc1fd001c, 0x01e00280);
266 * Clear framebuffer using Lime's drawing engine
267 * (draw blue rect. with white border around it)
269 /* Setup mode and fbbase, xres, fg, bg */
270 out_be32((void *)0xc1ff0420, 0x8300);
271 out_be32((void *)0xc1ff0440, 0x0000);
272 out_be32((void *)0xc1ff0444, 0x0280);
273 out_be32((void *)0xc1ff0480, 0x7fff);
274 out_be32((void *)0xc1ff0484, 0x0000);
275 /* Reset clipping rectangle */
276 out_be32((void *)0xc1ff0454, 0x0000);
277 out_be32((void *)0xc1ff0458, 0x0280);
278 out_be32((void *)0xc1ff045c, 0x0000);
279 out_be32((void *)0xc1ff0460, 0x01e0);
280 /* Draw white rect. */
281 out_be32((void *)0xc1ff04a0, 0x09410000);
282 out_be32((void *)0xc1ff04a0, 0x00000000);
283 out_be32((void *)0xc1ff04a0, 0x01e00280);
285 /* Draw blue rect. */
286 out_be32((void *)0xc1ff0480, 0x001f);
287 out_be32((void *)0xc1ff04a0, 0x09410000);
288 out_be32((void *)0xc1ff04a0, 0x00010001);
289 out_be32((void *)0xc1ff04a0, 0x01de027e);
291 /* Display enable, L0 layer */
292 out_be32((void *)0xc1fd0100, 0x80010f00);
294 /* TFT-LCD enable - PWM duty, lamp on */
295 out_be32((void *)0xc4000024, 0x64);
296 out_be32((void *)0xc4000020, 0x701);
303 char *s = getenv("serial#");
305 printf("Board: lwmon5");
316 #if defined(CFG_DRAM_TEST)
319 unsigned long *mem = (unsigned long *)0;
320 const unsigned long kend = (1024 / sizeof(unsigned long));
325 for (k = 0; k < CFG_MBYTES_SDRAM;
326 ++k, mem += (1024 / sizeof(unsigned long))) {
327 if ((k & 1023) == 0) {
328 printf("%3d MB\r", k / 1024);
331 memset(mem, 0xaaaaaaaa, 1024);
332 for (n = 0; n < kend; ++n) {
333 if (mem[n] != 0xaaaaaaaa) {
334 printf("SDRAM test fails at: %08x\n",
340 memset(mem, 0x55555555, 1024);
341 for (n = 0; n < kend; ++n) {
342 if (mem[n] != 0x55555555) {
343 printf("SDRAM test fails at: %08x\n",
349 printf("SDRAM test passes\n");
354 /*************************************************************************
357 * This routine is called just prior to registering the hose and gives
358 * the board the opportunity to check things. Returning a value of zero
359 * indicates that things are bad & PCI initialization should be aborted.
361 * Different boards may wish to customize the pci controller structure
362 * (add regions, override default access routines, etc) or perform
363 * certain pre-initialization actions.
365 ************************************************************************/
366 #if defined(CONFIG_PCI)
367 int pci_pre_init(struct pci_controller *hose)
371 /*-------------------------------------------------------------------------+
372 | Set priority for all PLB3 devices to 0.
373 | Set PLB3 arbiter to fair mode.
374 +-------------------------------------------------------------------------*/
375 mfsdr(sdr_amp1, addr);
376 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
377 addr = mfdcr(plb3_acr);
378 mtdcr(plb3_acr, addr | 0x80000000);
380 /*-------------------------------------------------------------------------+
381 | Set priority for all PLB4 devices to 0.
382 +-------------------------------------------------------------------------*/
383 mfsdr(sdr_amp0, addr);
384 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
385 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
386 mtdcr(plb4_acr, addr);
388 /*-------------------------------------------------------------------------+
389 | Set Nebula PLB4 arbiter to fair mode.
390 +-------------------------------------------------------------------------*/
392 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
393 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
394 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
395 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
396 mtdcr(plb0_acr, addr);
399 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
400 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
401 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
402 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
403 mtdcr(plb1_acr, addr);
407 #endif /* defined(CONFIG_PCI) */
409 /*************************************************************************
412 * The bootstrap configuration provides default settings for the pci
413 * inbound map (PIM). But the bootstrap config choices are limited and
414 * may not be sufficient for a given board.
416 ************************************************************************/
417 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
418 void pci_target_init(struct pci_controller *hose)
420 /*--------------------------------------------------------------------------+
421 * Set up Direct MMIO registers
422 *--------------------------------------------------------------------------*/
423 /*--------------------------------------------------------------------------+
424 | PowerPC440EPX PCI Master configuration.
425 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
426 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
427 | Use byte reversed out routines to handle endianess.
428 | Make this region non-prefetchable.
429 +--------------------------------------------------------------------------*/
430 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
431 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
432 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
433 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
434 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
436 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
437 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
438 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
439 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
440 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
442 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
443 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
444 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
445 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
447 /*--------------------------------------------------------------------------+
448 * Set up Configuration registers
449 *--------------------------------------------------------------------------*/
451 /* Program the board's subsystem id/vendor id */
452 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
453 CFG_PCI_SUBSYS_VENDORID);
454 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
456 /* Configure command register as bus master */
457 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
459 /* 240nS PCI clock */
460 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
462 /* No error reporting */
463 pci_write_config_word(0, PCI_ERREN, 0);
465 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
468 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
470 /*************************************************************************
473 ************************************************************************/
474 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
475 void pci_master_init(struct pci_controller *hose)
477 unsigned short temp_short;
479 /*--------------------------------------------------------------------------+
480 | Write the PowerPC440 EP PCI Configuration regs.
481 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
482 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
483 +--------------------------------------------------------------------------*/
484 pci_read_config_word(0, PCI_COMMAND, &temp_short);
485 pci_write_config_word(0, PCI_COMMAND,
486 temp_short | PCI_COMMAND_MASTER |
489 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
491 /*************************************************************************
494 * This routine is called to determine if a pci scan should be
495 * performed. With various hardware environments (especially cPCI and
496 * PPMC) it's insufficient to depend on the state of the arbiter enable
497 * bit in the strap register, or generic host/adapter assumptions.
499 * Rather than hard-code a bad assumption in the general 440 code, the
500 * 440 pci code requires the board to decide at runtime.
502 * Return 0 for adapter mode, non-zero for host (monarch) mode.
505 ************************************************************************/
506 #if defined(CONFIG_PCI)
507 int is_pci_host(struct pci_controller *hose)
509 /* Cactus is always configured as host. */
512 #endif /* defined(CONFIG_PCI) */
514 void hw_watchdog_reset(void)
519 * Toggle watchdog output
521 val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
522 gpio_write_bit(CFG_GPIO_WATCHDOG, val);
527 * Returns 1 if keys pressed to start the power-on long-running tests
528 * Called from board_init_f().
530 int post_hotkeys_pressed(void)