1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Logic PD, Inc.
5 * Author: Adam Ford <aford173@gmail.com>
7 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8 * and updates by Jagan Teki <jagan@amarulasolutions.com>
17 #include <fsl_esdhc_imx.h>
21 #include <linux/sizes.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/crm_regs.h>
24 #include <asm/arch/iomux.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/mx6-pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-imx/boot_mode.h>
29 #include <asm/mach-imx/iomux-v3.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
43 gd->ram_size = imx_ddr_size();
47 static iomux_v3_cfg_t const nand_pads[] = {
48 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
49 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
50 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
51 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
52 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
53 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
54 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
55 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
56 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
57 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
58 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
59 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
60 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
61 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
62 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
65 static void setup_nand_pins(void)
67 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
70 static int ar8031_phy_fixup(struct phy_device *phydev)
74 /* To enable AR8031 output a 125MHz clk from CLK_25M */
75 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
76 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
77 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
79 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
82 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
84 /* introduce tx clock delay */
85 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
86 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
88 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
93 int board_phy_config(struct phy_device *phydev)
95 ar8031_phy_fixup(phydev);
97 if (phydev->drv->config)
98 phydev->drv->config(phydev);
104 * Do not overwrite the console
105 * Use always serial for U-Boot console
107 int overwrite_console(void)
112 int board_early_init_f(void)
120 /* address of boot parameters */
121 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
125 int board_late_init(void)
127 env_set("board_name", "imx6logic");
130 env_set("board_rev", "MX6DQ");
131 if (!env_get("fdt_file"))
132 env_set("fdt_file", "imx6q-logicpd.dtb");
138 #ifdef CONFIG_SPL_BUILD
139 #include <asm/arch/mx6-ddr.h>
140 #include <asm/arch/mx6q-ddr.h>
142 #include <linux/libfdt.h>
144 #ifdef CONFIG_SPL_OS_BOOT
145 int spl_start_uboot(void)
147 /* break into full u-boot on 'c' */
148 if (serial_tstc() && serial_getc() == 'c')
155 void board_boot_order(u32 *spl_boot_list)
157 struct src *psrc = (struct src *)SRC_BASE_ADDR;
158 unsigned int reg = readl(&psrc->sbmr1) >> 11;
160 * Upon reading BOOT_CFG register the following map is done:
161 * Bit 11 and 12 of BOOT_CFG register can determine the current
167 reg &= 0x3; /* Only care about bottom 2 bits */
170 spl_boot_list[0] = BOOT_DEVICE_MMC1;
173 spl_boot_list[0] = BOOT_DEVICE_MMC2;
177 /* If we cannot find a valid MMC/SD card, try NAND */
178 spl_boot_list[1] = BOOT_DEVICE_NAND;
180 /* As a last resort, use serial downloader */
181 spl_boot_list[2] = BOOT_DEVICE_BOARD;
184 static void ccgr_init(void)
186 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
188 writel(0x00C03F3F, &ccm->CCGR0);
189 writel(0x0030FC03, &ccm->CCGR1);
190 writel(0x0FFFC000, &ccm->CCGR2);
191 writel(0x3FF00000, &ccm->CCGR3);
192 writel(0xFFFFF300, &ccm->CCGR4);
193 writel(0x0F0000F3, &ccm->CCGR5);
194 writel(0x00000FFF, &ccm->CCGR6);
197 static int mx6q_dcd_table[] = {
198 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
199 MX6_IOM_GRP_DDRPKE, 0x00000000,
200 MX6_IOM_DRAM_SDCLK_0, 0x00000030,
201 MX6_IOM_DRAM_SDCLK_1, 0x00000030,
202 MX6_IOM_DRAM_CAS, 0x00000030,
203 MX6_IOM_DRAM_RAS, 0x00000030,
204 MX6_IOM_GRP_ADDDS, 0x00000030,
205 MX6_IOM_DRAM_RESET, 0x00000030,
206 MX6_IOM_DRAM_SDBA2, 0x00000000,
207 MX6_IOM_DRAM_SDODT0, 0x00000030,
208 MX6_IOM_DRAM_SDODT1, 0x00000030,
209 MX6_IOM_GRP_CTLDS, 0x00000030,
210 MX6_IOM_DDRMODE_CTL, 0x00020000,
211 MX6_IOM_DRAM_SDQS0, 0x00000030,
212 MX6_IOM_DRAM_SDQS1, 0x00000030,
213 MX6_IOM_DRAM_SDQS2, 0x00000030,
214 MX6_IOM_DRAM_SDQS3, 0x00000030,
215 MX6_IOM_GRP_DDRMODE, 0x00020000,
216 MX6_IOM_GRP_B0DS, 0x00000030,
217 MX6_IOM_GRP_B1DS, 0x00000030,
218 MX6_IOM_GRP_B2DS, 0x00000030,
219 MX6_IOM_GRP_B3DS, 0x00000030,
220 MX6_IOM_DRAM_DQM0, 0x00000030,
221 MX6_IOM_DRAM_DQM1, 0x00000030,
222 MX6_IOM_DRAM_DQM2, 0x00000030,
223 MX6_IOM_DRAM_DQM3, 0x00000030,
224 MX6_MMDC_P0_MDSCR, 0x00008000,
225 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
226 MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
227 MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
228 MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
229 MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
230 MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
231 MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
232 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
233 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
234 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
235 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
236 MX6_MMDC_P0_MPMUR0, 0x00000800,
237 MX6_MMDC_P0_MDPDC, 0x00020036,
238 MX6_MMDC_P0_MDOTC, 0x09444040,
239 MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
240 MX6_MMDC_P0_MDCFG1, 0xFF328F64,
241 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
242 MX6_MMDC_P0_MDMISC, 0x00011740,
243 MX6_MMDC_P0_MDSCR, 0x00008000,
244 MX6_MMDC_P0_MDRWD, 0x000026D2,
245 MX6_MMDC_P0_MDOR, 0x00BE1023,
246 MX6_MMDC_P0_MDASP, 0x00000047,
247 MX6_MMDC_P0_MDCTL, 0x85190000,
248 MX6_MMDC_P0_MDSCR, 0x00888032,
249 MX6_MMDC_P0_MDSCR, 0x00008033,
250 MX6_MMDC_P0_MDSCR, 0x00008031,
251 MX6_MMDC_P0_MDSCR, 0x19408030,
252 MX6_MMDC_P0_MDSCR, 0x04008040,
253 MX6_MMDC_P0_MDREF, 0x00007800,
254 MX6_MMDC_P0_MPODTCTRL, 0x00000007,
255 MX6_MMDC_P0_MDPDC, 0x00025576,
256 MX6_MMDC_P0_MAPSR, 0x00011006,
257 MX6_MMDC_P0_MDSCR, 0x00000000,
258 /* enable AXI cache for VDOA/VPU/IPU */
260 MX6_IOMUXC_GPR4, 0xF00000CF,
261 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
262 MX6_IOMUXC_GPR6, 0x007F007F,
263 MX6_IOMUXC_GPR7, 0x007F007F,
266 static void ddr_init(int *table, int size)
270 for (i = 0; i < size / 2 ; i++)
271 writel(table[2 * i + 1], table[2 * i]);
274 static void spl_dram_init(void)
277 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
280 void board_init_f(ulong dummy)
282 /* DDR initialization */
285 /* setup AIPS and disable watchdog */
291 /* iomux and setup of uart and NAND pins */
292 board_early_init_f();
297 /* Enable device tree and early DM support*/
300 /* UART clocks enabled and gd valid - init serial console */
301 preloader_console_init();