board/logicpd/imx6/imx6logic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Logic PD, Inc.
   4  *
   5  * Author: Adam Ford <aford173@gmail.com>
   6  *
   7  * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
   8  * and updates by Jagan Teki <jagan@amarulasolutions.com>
   9  */
  10
  11 #include <common.h>
  12 #include <env.h>
  13 #include <miiphy.h>
  14 #include <input.h>
  15 #include <mmc.h>
  16 #include <fsl_esdhc_imx.h>
  17 #include <asm/io.h>
  18 #include <asm/gpio.h>
  19 #include <linux/sizes.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/arch/iomux.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/mx6-pins.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/mach-imx/boot_mode.h>
  27 #include <asm/mach-imx/iomux-v3.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  32         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  33         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  34
  35 #define NAND_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  36         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  37         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  38
  39 int dram_init(void)
  40 {
  41         gd->ram_size = imx_ddr_size();
  42         return 0;
  43 }
  44
  45 static iomux_v3_cfg_t const nand_pads[] = {
  46         MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  47         MX6_PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  48         MX6_PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  49         MX6_PAD_NANDF_WP_B__NAND_WP_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  50         MX6_PAD_NANDF_RB0__NAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
  51         MX6_PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  52         MX6_PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  53         MX6_PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  54         MX6_PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  55         MX6_PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  56         MX6_PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  57         MX6_PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  58         MX6_PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  59         MX6_PAD_SD4_CLK__NAND_WE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  60         MX6_PAD_SD4_CMD__NAND_RE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
  61 };
  62
  63 static void setup_nand_pins(void)
  64 {
  65         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  66 }
  67
  68 static int ar8031_phy_fixup(struct phy_device *phydev)
  69 {
  70         unsigned short val;
  71
  72         /* To enable AR8031 output a 125MHz clk from CLK_25M */
  73         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  74         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  75         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  76
  77         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  78         val &= 0xffe3;
  79         val |= 0x18;
  80         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  81
  82         /* introduce tx clock delay */
  83         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  84         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  85         val |= 0x0100;
  86         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  87
  88         return 0;
  89 }
  90
  91 int board_phy_config(struct phy_device *phydev)
  92 {
  93         ar8031_phy_fixup(phydev);
  94
  95         if (phydev->drv->config)
  96                 phydev->drv->config(phydev);
  97
  98         return 0;
  99 }
 100
 101 /*
 102  * Do not overwrite the console
 103  * Use always serial for U-Boot console
 104  */
 105 int overwrite_console(void)
 106 {
 107         return 1;
 108 }
 109
 110 int board_early_init_f(void)
 111 {
 112         setup_nand_pins();
 113         return 0;
 114 }
 115
 116 int board_init(void)
 117 {
 118         /* address of boot parameters */
 119         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 120         return 0;
 121 }
 122
 123 int board_late_init(void)
 124 {
 125         env_set("board_name", "imx6logic");
 126
 127         if (is_mx6dq()) {
 128                 env_set("board_rev", "MX6DQ");
 129                 if (!env_get("fdt_file"))
 130                         env_set("fdt_file", "imx6q-logicpd.dtb");
 131         }
 132
 133         return 0;
 134 }
 135
 136 #ifdef CONFIG_SPL_BUILD
 137 #include <asm/arch/mx6-ddr.h>
 138 #include <asm/arch/mx6q-ddr.h>
 139 #include <spl.h>
 140 #include <linux/libfdt.h>
 141
 142 #ifdef CONFIG_SPL_OS_BOOT
 143 int spl_start_uboot(void)
 144 {
 145         /* break into full u-boot on 'c' */
 146         if (serial_tstc() && serial_getc() == 'c')
 147                 return 1;
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 void board_boot_order(u32 *spl_boot_list)
 154 {
 155         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 156         unsigned int reg = readl(&psrc->sbmr1) >> 11;
 157         /*
 158          * Upon reading BOOT_CFG register the following map is done:
 159          * Bit 11 and 12 of BOOT_CFG register can determine the current
 160          * mmc port
 161          * 0x1                  SD1-SOM
 162          * 0x2                  SD2-Baseboard
 163          */
 164
 165         reg &= 0x3; /* Only care about bottom 2 bits */
 166         switch (reg) {
 167         case 0:
 168                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 169                 break;
 170         case 1:
 171                 spl_boot_list[0] = BOOT_DEVICE_MMC2;
 172                 break;
 173         }
 174
 175         /* If we cannot find a valid MMC/SD card, try NAND */
 176         spl_boot_list[1] = BOOT_DEVICE_NAND;
 177
 178         /* As a last resort, use serial downloader */
 179         spl_boot_list[2] = BOOT_DEVICE_BOARD;
 180 }
 181
 182 static void ccgr_init(void)
 183 {
 184         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 185
 186         writel(0x00C03F3F, &ccm->CCGR0);
 187         writel(0x0030FC03, &ccm->CCGR1);
 188         writel(0x0FFFC000, &ccm->CCGR2);
 189         writel(0x3FF00000, &ccm->CCGR3);
 190         writel(0xFFFFF300, &ccm->CCGR4);
 191         writel(0x0F0000F3, &ccm->CCGR5);
 192         writel(0x00000FFF, &ccm->CCGR6);
 193 }
 194
 195 static int mx6q_dcd_table[] = {
 196         MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 197         MX6_IOM_GRP_DDRPKE, 0x00000000,
 198         MX6_IOM_DRAM_SDCLK_0, 0x00000030,
 199         MX6_IOM_DRAM_SDCLK_1, 0x00000030,
 200         MX6_IOM_DRAM_CAS, 0x00000030,
 201         MX6_IOM_DRAM_RAS, 0x00000030,
 202         MX6_IOM_GRP_ADDDS, 0x00000030,
 203         MX6_IOM_DRAM_RESET, 0x00000030,
 204         MX6_IOM_DRAM_SDBA2, 0x00000000,
 205         MX6_IOM_DRAM_SDODT0, 0x00000030,
 206         MX6_IOM_DRAM_SDODT1, 0x00000030,
 207         MX6_IOM_GRP_CTLDS, 0x00000030,
 208         MX6_IOM_DDRMODE_CTL, 0x00020000,
 209         MX6_IOM_DRAM_SDQS0, 0x00000030,
 210         MX6_IOM_DRAM_SDQS1, 0x00000030,
 211         MX6_IOM_DRAM_SDQS2, 0x00000030,
 212         MX6_IOM_DRAM_SDQS3, 0x00000030,
 213         MX6_IOM_GRP_DDRMODE, 0x00020000,
 214         MX6_IOM_GRP_B0DS, 0x00000030,
 215         MX6_IOM_GRP_B1DS, 0x00000030,
 216         MX6_IOM_GRP_B2DS, 0x00000030,
 217         MX6_IOM_GRP_B3DS, 0x00000030,
 218         MX6_IOM_DRAM_DQM0, 0x00000030,
 219         MX6_IOM_DRAM_DQM1, 0x00000030,
 220         MX6_IOM_DRAM_DQM2, 0x00000030,
 221         MX6_IOM_DRAM_DQM3, 0x00000030,
 222         MX6_MMDC_P0_MDSCR, 0x00008000,
 223         MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 224         MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
 225         MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
 226         MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
 227         MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
 228         MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
 229         MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
 230         MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 231         MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 232         MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 233         MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 234         MX6_MMDC_P0_MPMUR0, 0x00000800,
 235         MX6_MMDC_P0_MDPDC, 0x00020036,
 236         MX6_MMDC_P0_MDOTC, 0x09444040,
 237         MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
 238         MX6_MMDC_P0_MDCFG1, 0xFF328F64,
 239         MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 240         MX6_MMDC_P0_MDMISC, 0x00011740,
 241         MX6_MMDC_P0_MDSCR, 0x00008000,
 242         MX6_MMDC_P0_MDRWD, 0x000026D2,
 243         MX6_MMDC_P0_MDOR, 0x00BE1023,
 244         MX6_MMDC_P0_MDASP, 0x00000047,
 245         MX6_MMDC_P0_MDCTL, 0x85190000,
 246         MX6_MMDC_P0_MDSCR, 0x00888032,
 247         MX6_MMDC_P0_MDSCR, 0x00008033,
 248         MX6_MMDC_P0_MDSCR, 0x00008031,
 249         MX6_MMDC_P0_MDSCR, 0x19408030,
 250         MX6_MMDC_P0_MDSCR, 0x04008040,
 251         MX6_MMDC_P0_MDREF, 0x00007800,
 252         MX6_MMDC_P0_MPODTCTRL, 0x00000007,
 253         MX6_MMDC_P0_MDPDC, 0x00025576,
 254         MX6_MMDC_P0_MAPSR, 0x00011006,
 255         MX6_MMDC_P0_MDSCR, 0x00000000,
 256         /* enable AXI cache for VDOA/VPU/IPU */
 257
 258         MX6_IOMUXC_GPR4, 0xF00000CF,
 259         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 260         MX6_IOMUXC_GPR6, 0x007F007F,
 261         MX6_IOMUXC_GPR7, 0x007F007F,
 262 };
 263
 264 static void ddr_init(int *table, int size)
 265 {
 266         int i;
 267
 268         for (i = 0; i < size / 2 ; i++)
 269                 writel(table[2 * i + 1], table[2 * i]);
 270 }
 271
 272 static void spl_dram_init(void)
 273 {
 274         if (is_mx6dq())
 275                 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
 276 }
 277
 278 void board_init_f(ulong dummy)
 279 {
 280         /* DDR initialization */
 281         spl_dram_init();
 282
 283         /* setup AIPS and disable watchdog */
 284         arch_cpu_init();
 285
 286         ccgr_init();
 287         gpr_init();
 288
 289         /* iomux and setup of uart and NAND pins */
 290         board_early_init_f();
 291
 292         /* setup GP timer */
 293         timer_init();
 294
 295         /* Enable device tree and early DM support*/
 296         spl_early_init();
 297
 298         /* UART clocks enabled and gd valid - init serial console */
 299         preloader_console_init();
 300 }
 301 #endif