1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Logic PD, Inc.
5 * Author: Adam Ford <aford173@gmail.com>
7 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8 * and updates by Jagan Teki <jagan@amarulasolutions.com>
16 #include <fsl_esdhc_imx.h>
19 #include <linux/sizes.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/iomux.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/mx6-pins.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/mach-imx/boot_mode.h>
27 #include <asm/mach-imx/iomux-v3.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
41 gd->ram_size = imx_ddr_size();
45 static iomux_v3_cfg_t const uart1_pads[] = {
46 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
47 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
50 static iomux_v3_cfg_t const uart2_pads[] = {
51 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
53 MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
54 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
57 static iomux_v3_cfg_t const uart3_pads[] = {
58 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
59 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
60 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
64 static void setup_iomux_uart(void)
66 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
67 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
68 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
71 static iomux_v3_cfg_t const nand_pads[] = {
72 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
73 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
78 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
79 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
86 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
89 static void setup_nand_pins(void)
91 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
94 static int ar8031_phy_fixup(struct phy_device *phydev)
98 /* To enable AR8031 output a 125MHz clk from CLK_25M */
99 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
100 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
101 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
103 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
106 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
108 /* introduce tx clock delay */
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
110 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
112 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
117 int board_phy_config(struct phy_device *phydev)
119 ar8031_phy_fixup(phydev);
121 if (phydev->drv->config)
122 phydev->drv->config(phydev);
128 * Do not overwrite the console
129 * Use always serial for U-Boot console
131 int overwrite_console(void)
136 int board_early_init_f(void)
145 /* address of boot parameters */
146 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
150 int board_late_init(void)
152 env_set("board_name", "imx6logic");
155 env_set("board_rev", "MX6DQ");
156 if (!env_get("fdt_file"))
157 env_set("fdt_file", "imx6q-logicpd.dtb");
163 #ifdef CONFIG_SPL_BUILD
164 #include <asm/arch/mx6-ddr.h>
165 #include <asm/arch/mx6q-ddr.h>
167 #include <linux/libfdt.h>
169 #ifdef CONFIG_SPL_OS_BOOT
170 int spl_start_uboot(void)
172 /* break into full u-boot on 'c' */
173 if (serial_tstc() && serial_getc() == 'c')
181 #define USDHC_PAD_CTRL \
182 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
183 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
185 static iomux_v3_cfg_t const usdhc1_pads[] = {
186 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
187 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
190 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
191 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 static iomux_v3_cfg_t const usdhc2_pads[] = {
195 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
201 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
204 #ifdef CONFIG_FSL_ESDHC_IMX
205 struct fsl_esdhc_cfg usdhc_cfg[] = {
206 {USDHC1_BASE_ADDR}, /* SOM */
207 {USDHC2_BASE_ADDR} /* Baseboard */
210 int board_mmc_init(bd_t *bis)
212 struct src *psrc = (struct src *)SRC_BASE_ADDR;
213 unsigned int reg = readl(&psrc->sbmr1) >> 11;
215 * Upon reading BOOT_CFG register the following map is done:
216 * Bit 11 and 12 of BOOT_CFG register can determine the current
222 reg &= 0x3; /* Only care about bottom 2 bits */
226 SETUP_IOMUX_PADS(usdhc1_pads);
229 SETUP_IOMUX_PADS(usdhc2_pads);
238 static void ccgr_init(void)
240 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
242 writel(0x00C03F3F, &ccm->CCGR0);
243 writel(0x0030FC03, &ccm->CCGR1);
244 writel(0x0FFFC000, &ccm->CCGR2);
245 writel(0x3FF00000, &ccm->CCGR3);
246 writel(0xFFFFF300, &ccm->CCGR4);
247 writel(0x0F0000F3, &ccm->CCGR5);
248 writel(0x00000FFF, &ccm->CCGR6);
251 static int mx6q_dcd_table[] = {
252 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
253 MX6_IOM_GRP_DDRPKE, 0x00000000,
254 MX6_IOM_DRAM_SDCLK_0, 0x00000030,
255 MX6_IOM_DRAM_SDCLK_1, 0x00000030,
256 MX6_IOM_DRAM_CAS, 0x00000030,
257 MX6_IOM_DRAM_RAS, 0x00000030,
258 MX6_IOM_GRP_ADDDS, 0x00000030,
259 MX6_IOM_DRAM_RESET, 0x00000030,
260 MX6_IOM_DRAM_SDBA2, 0x00000000,
261 MX6_IOM_DRAM_SDODT0, 0x00000030,
262 MX6_IOM_DRAM_SDODT1, 0x00000030,
263 MX6_IOM_GRP_CTLDS, 0x00000030,
264 MX6_IOM_DDRMODE_CTL, 0x00020000,
265 MX6_IOM_DRAM_SDQS0, 0x00000030,
266 MX6_IOM_DRAM_SDQS1, 0x00000030,
267 MX6_IOM_DRAM_SDQS2, 0x00000030,
268 MX6_IOM_DRAM_SDQS3, 0x00000030,
269 MX6_IOM_GRP_DDRMODE, 0x00020000,
270 MX6_IOM_GRP_B0DS, 0x00000030,
271 MX6_IOM_GRP_B1DS, 0x00000030,
272 MX6_IOM_GRP_B2DS, 0x00000030,
273 MX6_IOM_GRP_B3DS, 0x00000030,
274 MX6_IOM_DRAM_DQM0, 0x00000030,
275 MX6_IOM_DRAM_DQM1, 0x00000030,
276 MX6_IOM_DRAM_DQM2, 0x00000030,
277 MX6_IOM_DRAM_DQM3, 0x00000030,
278 MX6_MMDC_P0_MDSCR, 0x00008000,
279 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
280 MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
281 MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
282 MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
283 MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
284 MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
285 MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
286 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
287 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
288 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
289 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
290 MX6_MMDC_P0_MPMUR0, 0x00000800,
291 MX6_MMDC_P0_MDPDC, 0x00020036,
292 MX6_MMDC_P0_MDOTC, 0x09444040,
293 MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
294 MX6_MMDC_P0_MDCFG1, 0xFF328F64,
295 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
296 MX6_MMDC_P0_MDMISC, 0x00011740,
297 MX6_MMDC_P0_MDSCR, 0x00008000,
298 MX6_MMDC_P0_MDRWD, 0x000026D2,
299 MX6_MMDC_P0_MDOR, 0x00BE1023,
300 MX6_MMDC_P0_MDASP, 0x00000047,
301 MX6_MMDC_P0_MDCTL, 0x85190000,
302 MX6_MMDC_P0_MDSCR, 0x00888032,
303 MX6_MMDC_P0_MDSCR, 0x00008033,
304 MX6_MMDC_P0_MDSCR, 0x00008031,
305 MX6_MMDC_P0_MDSCR, 0x19408030,
306 MX6_MMDC_P0_MDSCR, 0x04008040,
307 MX6_MMDC_P0_MDREF, 0x00007800,
308 MX6_MMDC_P0_MPODTCTRL, 0x00000007,
309 MX6_MMDC_P0_MDPDC, 0x00025576,
310 MX6_MMDC_P0_MAPSR, 0x00011006,
311 MX6_MMDC_P0_MDSCR, 0x00000000,
312 /* enable AXI cache for VDOA/VPU/IPU */
314 MX6_IOMUXC_GPR4, 0xF00000CF,
315 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
316 MX6_IOMUXC_GPR6, 0x007F007F,
317 MX6_IOMUXC_GPR7, 0x007F007F,
320 static void ddr_init(int *table, int size)
324 for (i = 0; i < size / 2 ; i++)
325 writel(table[2 * i + 1], table[2 * i]);
328 static void spl_dram_init(void)
331 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
334 void board_init_f(ulong dummy)
336 /* DDR initialization */
339 /* setup AIPS and disable watchdog */
345 /* iomux and setup of uart and NAND pins */
346 board_early_init_f();
351 /* UART clocks enabled and gd valid - init serial console */
352 preloader_console_init();