board/liebherr/mccmon6/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Wandboard
   4  * Author: Tungyi Lin <tungyilin1127@gmail.com>
   5  *         Richard Hu <hakahu@gmail.com>
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/video.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc_imx.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <serial.h>
  22 #include <spl.h>
  23
  24 #include <asm/arch/mx6-ddr.h>
  25 /*
  26  * Driving strength:
  27  *   0x30 == 40 Ohm
  28  *   0x28 == 48 Ohm
  29  */
  30
  31 #define IMX6DQ_DRIVE_STRENGTH           0x30
  32 #define IMX6SDL_DRIVE_STRENGTH          0x28
  33
  34 /* configure MX6Q/DUAL mmdc DDR io registers */
  35 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  36         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  37         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  38         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  39         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  40         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  41         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  42         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  43         .dram_sdba2 = 0x00000000,
  44         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  45         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  46         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  47         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  48         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  53         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  58         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  59         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  60         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  61         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  62 };
  63
  64 /* configure MX6Q/DUAL mmdc GRP io registers */
  65 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  66         .grp_ddr_type = 0x000c0000,
  67         .grp_ddrmode_ctl = 0x00020000,
  68         .grp_ddrpke = 0x00000000,
  69         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  70         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  71         .grp_ddrmode = 0x00020000,
  72         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  73         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  74         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  75         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  76         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  77         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  78         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  79         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  80 };
  81
  82 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  83 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  84         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  85         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  86         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  87         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  88         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  89         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  90         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  91         .dram_sdba2 = 0x00000000,
  92         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  93         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  94         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  95         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  96         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  97         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  98         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  99         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 100         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 101         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 102         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 103         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 104         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 105         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 106         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 107         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 108         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 109         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 110 };
 111
 112 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 113 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 114         .grp_ddr_type = 0x000c0000,
 115         .grp_ddrmode_ctl = 0x00020000,
 116         .grp_ddrpke = 0x00000000,
 117         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 118         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 119         .grp_ddrmode = 0x00020000,
 120         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 121         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 122         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 123         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 124         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 125         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 126         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 127         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 128 };
 129
 130 /* H5T04G63AFR-PB */
 131 static struct mx6_ddr3_cfg h5t04g63afr = {
 132         .mem_speed = 1600,
 133         .density = 4,
 134         .width = 16,
 135         .banks = 8,
 136         .rowaddr = 15,
 137         .coladdr = 10,
 138         .pagesz = 2,
 139         .trcd = 1375,
 140         .trcmin = 4875,
 141         .trasmin = 3500,
 142 };
 143
 144 /* H5TQ2G63DFR-H9 */
 145 static struct mx6_ddr3_cfg h5tq2g63dfr = {
 146         .mem_speed = 1333,
 147         .density = 2,
 148         .width = 16,
 149         .banks = 8,
 150         .rowaddr = 14,
 151         .coladdr = 10,
 152         .pagesz = 2,
 153         .trcd = 1350,
 154         .trcmin = 4950,
 155         .trasmin = 3600,
 156 };
 157
 158 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
 159         .p0_mpwldectrl0 = 0x001f001f,
 160         .p0_mpwldectrl1 = 0x001f001f,
 161         .p1_mpwldectrl0 = 0x001f001f,
 162         .p1_mpwldectrl1 = 0x001f001f,
 163         .p0_mpdgctrl0 = 0x4301030d,
 164         .p0_mpdgctrl1 = 0x03020277,
 165         .p1_mpdgctrl0 = 0x4300030a,
 166         .p1_mpdgctrl1 = 0x02780248,
 167         .p0_mprddlctl = 0x4536393b,
 168         .p1_mprddlctl = 0x36353441,
 169         .p0_mpwrdlctl = 0x41414743,
 170         .p1_mpwrdlctl = 0x462f453f,
 171 };
 172
 173 /* DDR 64bit 2GB */
 174 static struct mx6_ddr_sysinfo mem_q = {
 175         .dsize          = 2,
 176         .cs1_mirror     = 0,
 177         /* config for full 4GB range so that get_mem_size() works */
 178         .cs_density     = 32,
 179         .ncs            = 1,
 180         .bi_on          = 1,
 181         .rtt_nom        = 1,
 182         .rtt_wr         = 0,
 183         .ralat          = 5,
 184         .walat          = 0,
 185         .mif3_mode      = 3,
 186         .rst_to_cke     = 0x23,
 187         .sde_to_rst     = 0x10,
 188 };
 189
 190 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 191         .p0_mpwldectrl0 = 0x001f001f,
 192         .p0_mpwldectrl1 = 0x001f001f,
 193         .p1_mpwldectrl0 = 0x001f001f,
 194         .p1_mpwldectrl1 = 0x001f001f,
 195         .p0_mpdgctrl0 = 0x420e020e,
 196         .p0_mpdgctrl1 = 0x02000200,
 197         .p1_mpdgctrl0 = 0x42020202,
 198         .p1_mpdgctrl1 = 0x01720172,
 199         .p0_mprddlctl = 0x494c4f4c,
 200         .p1_mprddlctl = 0x4a4c4c49,
 201         .p0_mpwrdlctl = 0x3f3f3133,
 202         .p1_mpwrdlctl = 0x39373f2e,
 203 };
 204
 205 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
 206         .p0_mpwldectrl0 = 0x0040003c,
 207         .p0_mpwldectrl1 = 0x0032003e,
 208         .p0_mpdgctrl0 = 0x42350231,
 209         .p0_mpdgctrl1 = 0x021a0218,
 210         .p0_mprddlctl = 0x4b4b4e49,
 211         .p0_mpwrdlctl = 0x3f3f3035,
 212 };
 213
 214 /* DDR 64bit 1GB */
 215 static struct mx6_ddr_sysinfo mem_dl = {
 216         .dsize          = 2,
 217         .cs1_mirror     = 0,
 218         /* config for full 4GB range so that get_mem_size() works */
 219         .cs_density     = 32,
 220         .ncs            = 1,
 221         .bi_on          = 1,
 222         .rtt_nom        = 1,
 223         .rtt_wr         = 0,
 224         .ralat          = 5,
 225         .walat          = 0,
 226         .mif3_mode      = 3,
 227         .rst_to_cke     = 0x23,
 228         .sde_to_rst     = 0x10,
 229 };
 230
 231 /* DDR 32bit 512MB */
 232 static struct mx6_ddr_sysinfo mem_s = {
 233         .dsize          = 1,
 234         .cs1_mirror     = 0,
 235         /* config for full 4GB range so that get_mem_size() works */
 236         .cs_density     = 32,
 237         .ncs            = 1,
 238         .bi_on          = 1,
 239         .rtt_nom        = 1,
 240         .rtt_wr         = 0,
 241         .ralat          = 5,
 242         .walat          = 0,
 243         .mif3_mode      = 3,
 244         .rst_to_cke     = 0x23,
 245         .sde_to_rst     = 0x10,
 246 };
 247
 248 static void ccgr_init(void)
 249 {
 250         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 251
 252         writel(0x00C03F3F, &ccm->CCGR0);
 253         writel(0x0030FC03, &ccm->CCGR1);
 254         writel(0x0FFFC000, &ccm->CCGR2);
 255         writel(0x3FF00000, &ccm->CCGR3);
 256         writel(0x00FFF300, &ccm->CCGR4);
 257         writel(0x0F0000C3, &ccm->CCGR5);
 258         writel(0x000003FF, &ccm->CCGR6);
 259 }
 260
 261 static void spl_dram_init(void)
 262 {
 263         if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 264                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 265                 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
 266         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 267                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 268                 mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
 269         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 270                 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 271                 mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
 272         }
 273
 274         udelay(100);
 275 }
 276
 277 static void setup_spi(void)
 278 {
 279         enable_spi_clk(true, 2);
 280 }
 281
 282 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
 283         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
 284         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 285
 286 static iomux_v3_cfg_t const uart1_pads[] = {
 287         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 288         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 289 };
 290
 291 static void setup_iomux_uart(void)
 292 {
 293         SETUP_IOMUX_PADS(uart1_pads);
 294 }
 295
 296 void board_init_f(ulong dummy)
 297 {
 298         ccgr_init();
 299
 300         /* setup AIPS and disable watchdog */
 301         arch_cpu_init();
 302
 303         gpr_init();
 304
 305         /* iomux */
 306         setup_iomux_uart();
 307
 308         /* setup GP timer */
 309         timer_init();
 310
 311         /* UART clocks enabled and gd valid - init serial console */
 312         preloader_console_init();
 313
 314         /* enable ECSPI clocks */
 315         setup_spi();
 316
 317         /* DDR initialization */
 318         spl_dram_init();
 319 }
 320
 321 void board_boot_order(u32 *spl_boot_list)
 322 {
 323         switch (spl_boot_device()) {
 324         case BOOT_DEVICE_MMC2:
 325         case BOOT_DEVICE_MMC1:
 326                 spl_boot_list[0] = BOOT_DEVICE_MMC2;
 327                 spl_boot_list[1] = BOOT_DEVICE_MMC1;
 328                 break;
 329
 330         case BOOT_DEVICE_NOR:
 331                 spl_boot_list[0] = BOOT_DEVICE_NOR;
 332                 break;
 333         }
 334 }
 335
 336 #ifdef CONFIG_SPL_LOAD_FIT
 337 int board_fit_config_name_match(const char *name)
 338 {
 339         return 0;
 340 }
 341 #endif
 342
 343 #ifdef CONFIG_SPL_OS_BOOT
 344 int spl_start_uboot(void)
 345 {
 346         char s[16];
 347         int ret;
 348         /*
 349          * We use BOOT_DEVICE_MMC1, but SD card is connected
 350          * to MMC2
 351          *
 352          * Correct "mapping" is delivered in board defined
 353          * board_boot_order() function.
 354          *
 355          * SD card boot is regarded as a "development" one,
 356          * hence we _always_ go through the u-boot.
 357          *
 358          */
 359         if (spl_boot_device() == BOOT_DEVICE_MMC1)
 360                 return 1;
 361
 362         /* break into full u-boot on 'c' */
 363         if (serial_tstc() && serial_getc() == 'c')
 364                 return 1;
 365
 366         env_init();
 367         ret = env_get_f("boot_os", s, sizeof(s));
 368         if ((ret != -1) && (strcmp(s, "no") == 0))
 369                 return 1;
 370
 371         /*
 372          * Check if SWUpdate recovery needs to be started
 373          *
 374          * recovery_status = NULL (not set - ret == -1) -> normal operation
 375          *
 376          * recovery_status = progress or
 377          * recovery_status = failed   or
 378          * recovery_status = <any value> -> start SWUpdate
 379          *
 380          */
 381         ret = env_get_f("recovery_status", s, sizeof(s));
 382         if (ret != -1)
 383                 return 1;
 384
 385         return 0;
 386 }
 387 #endif /* CONFIG_SPL_OS_BOOT */
 388
 389 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
 390         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
 391         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 392
 393 #define NOR_WP                  IMX_GPIO_NR(1, 1)
 394
 395 static iomux_v3_cfg_t const eimnor_pads[] = {
 396         IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 397         IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 398         IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 399         IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 400         IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 401         IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 402         IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 403         IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 404         IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 405         IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 406         IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 407         IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 408         IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 409         IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 410         IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 411         IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 412         IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 413         IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 414         IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 415         IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 416         IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 417         IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 418         IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 419         IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 420         IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 421         IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 422         IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 423         IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 424         IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 425         IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 426         IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 427         IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 428         IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 429         IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 430         IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 431         IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 432         IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 433         IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 434         IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 435         IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 436         IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 437         IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 438         IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 439         IOMUX_PADS(PAD_EIM_RW__EIM_RW           | MUX_PAD_CTRL(NO_PAD_CTRL)),
 440         IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 441         IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 442 };
 443
 444 static void eimnor_cs_setup(void)
 445 {
 446         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 447
 448         /* NOR configuration */
 449         writel(0x00620181, &weim_regs->cs0gcr1);
 450         writel(0x00000001, &weim_regs->cs0gcr2);
 451         writel(0x0b020000, &weim_regs->cs0rcr1);
 452         writel(0x0000b000, &weim_regs->cs0rcr2);
 453         writel(0x0804a240, &weim_regs->cs0wcr1);
 454         writel(0x00000000, &weim_regs->cs0wcr2);
 455
 456         writel(0x00000120, &weim_regs->wcr);
 457         writel(0x00000010, &weim_regs->wiar);
 458         writel(0x00000000, &weim_regs->ear);
 459
 460         set_chipselect_size(CS0_128);
 461 }
 462
 463 static void setup_eimnor(void)
 464 {
 465         SETUP_IOMUX_PADS(eimnor_pads);
 466         gpio_direction_output(NOR_WP, 1);
 467
 468         enable_eim_clk(1);
 469         eimnor_cs_setup();
 470 }
 471
 472 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 473         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
 474         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 475
 476 #define USDHC2_CD_GPIO          IMX_GPIO_NR(1, 4)
 477
 478 static iomux_v3_cfg_t const usdhc2_pads[] = {
 479         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 480         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 481         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 482         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 483         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 484         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 485         /* Carrier MicroSD Card Detect */
 486         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 487 };
 488
 489 static iomux_v3_cfg_t const usdhc3_pads[] = {
 490         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 491         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 492         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 493         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 494         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 495         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 496         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 497         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 498         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 499         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 500         IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 501 };
 502
 503 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 504         {USDHC3_BASE_ADDR},
 505         {USDHC2_BASE_ADDR},
 506 };
 507
 508 int board_mmc_getcd(struct mmc *mmc)
 509 {
 510         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 511         int ret = 0;
 512
 513         switch (cfg->esdhc_base) {
 514         case USDHC2_BASE_ADDR:
 515                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 516                 break;
 517         case USDHC3_BASE_ADDR:
 518                 /*
 519                  * eMMC don't have card detect pin - since it is soldered to the
 520                  * PCB board
 521                  */
 522                 ret = 1;
 523                 break;
 524         }
 525         return ret;
 526 }
 527
 528 int board_mmc_init(bd_t *bis)
 529 {
 530         int ret;
 531         u32 index = 0;
 532
 533         /*
 534          * MMC MAP
 535          * (U-Boot device node)    (Physical Port)
 536          * mmc0                    Soldered on board eMMC device
 537          * mmc1                    MicroSD card
 538          */
 539         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 540                 switch (index) {
 541                 case 0:
 542                         SETUP_IOMUX_PADS(usdhc3_pads);
 543                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 544                         usdhc_cfg[0].max_bus_width = 8;
 545                         break;
 546                 case 1:
 547                         SETUP_IOMUX_PADS(usdhc2_pads);
 548                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 549                         usdhc_cfg[1].max_bus_width = 4;
 550                         gpio_direction_input(USDHC2_CD_GPIO);
 551                         break;
 552                 default:
 553                         printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
 554                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 555                         return -EINVAL;
 556                 }
 557
 558                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 559                 if (ret)
 560                         return ret;
 561         }
 562
 563         return 0;
 564 }
 565
 566 #ifdef CONFIG_SPL_BOARD_INIT
 567 #define DISPLAY_EN              IMX_GPIO_NR(1, 2)
 568 void spl_board_init(void)
 569 {
 570         setup_eimnor();
 571
 572         gpio_direction_output(DISPLAY_EN, 1);
 573 }
 574 #endif /* CONFIG_SPL_BOARD_INIT */