1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016-2017
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
18 #include <fsl_esdhc_imx.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
28 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
29 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
31 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
32 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
33 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
39 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
40 #define NOR_WP IMX_GPIO_NR(1, 1)
41 #define DISPLAY_EN IMX_GPIO_NR(1, 2)
45 gd->ram_size = imx_ddr_size();
50 static iomux_v3_cfg_t const uart1_pads[] = {
51 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
52 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
55 static iomux_v3_cfg_t const usdhc2_pads[] = {
56 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 /* Carrier MicroSD Card Detect */
63 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
66 static iomux_v3_cfg_t const usdhc3_pads[] = {
67 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
68 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
69 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
70 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
71 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
72 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 static void setup_iomux_uart(void)
82 SETUP_IOMUX_PADS(uart1_pads);
85 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
90 int board_mmc_getcd(struct mmc *mmc)
92 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
95 switch (cfg->esdhc_base) {
96 case USDHC2_BASE_ADDR:
97 ret = !gpio_get_value(USDHC2_CD_GPIO);
99 case USDHC3_BASE_ADDR:
101 * eMMC don't have card detect pin - since it is soldered to the
110 int board_mmc_init(bd_t *bis)
117 * (U-Boot device node) (Physical Port)
118 * mmc0 Soldered on board eMMC device
121 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
124 SETUP_IOMUX_PADS(usdhc3_pads);
125 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
126 usdhc_cfg[0].max_bus_width = 8;
129 SETUP_IOMUX_PADS(usdhc2_pads);
130 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
131 usdhc_cfg[1].max_bus_width = 4;
132 gpio_direction_input(USDHC2_CD_GPIO);
135 printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
136 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
140 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
148 static iomux_v3_cfg_t const eimnor_pads[] = {
149 IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
150 IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
151 IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
152 IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
153 IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
154 IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
155 IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
156 IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
157 IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
158 IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
159 IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
160 IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
161 IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
162 IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
163 IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
164 IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
165 IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
166 IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
167 IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
168 IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
169 IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
170 IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
171 IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
172 IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
173 IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
174 IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
175 IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
176 IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
177 IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
178 IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
179 IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
180 IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
184 IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
185 IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
190 IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
191 IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
194 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
197 static void eimnor_cs_setup(void)
199 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
202 /* NOR configuration */
203 writel(0x00620181, &weim_regs->cs0gcr1);
204 writel(0x00000001, &weim_regs->cs0gcr2);
205 writel(0x0b020000, &weim_regs->cs0rcr1);
206 writel(0x0000b000, &weim_regs->cs0rcr2);
207 writel(0x0804a240, &weim_regs->cs0wcr1);
208 writel(0x00000000, &weim_regs->cs0wcr2);
210 writel(0x00000120, &weim_regs->wcr);
211 writel(0x00000010, &weim_regs->wiar);
212 writel(0x00000000, &weim_regs->ear);
214 set_chipselect_size(CS0_128);
217 static void setup_eimnor(void)
219 SETUP_IOMUX_PADS(eimnor_pads);
220 gpio_direction_output(NOR_WP, 1);
226 int board_early_init_f(void)
235 /* address of boot parameters */
236 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
238 gpio_direction_output(DISPLAY_EN, 1);
245 int board_late_init(void)
247 env_set("board_name", "mccmon6");
254 puts("Board: MCCMON6\n");
259 #ifdef CONFIG_SPL_BOARD_INIT
260 void spl_board_init(void)
264 gpio_direction_output(DISPLAY_EN, 1);
266 #endif /* CONFIG_SPL_BOARD_INIT */
268 #ifdef CONFIG_SPL_BUILD
269 void board_boot_order(u32 *spl_boot_list)
271 switch (spl_boot_device()) {
272 case BOOT_DEVICE_MMC2:
273 case BOOT_DEVICE_MMC1:
274 spl_boot_list[0] = BOOT_DEVICE_MMC2;
275 spl_boot_list[1] = BOOT_DEVICE_MMC1;
278 case BOOT_DEVICE_NOR:
279 spl_boot_list[0] = BOOT_DEVICE_NOR;
283 #endif /* CONFIG_SPL_BUILD */
285 #ifdef CONFIG_SPL_OS_BOOT
286 int spl_start_uboot(void)
291 * We use BOOT_DEVICE_MMC1, but SD card is connected
294 * Correct "mapping" is delivered in board defined
295 * board_boot_order() function.
297 * SD card boot is regarded as a "development" one,
298 * hence we _always_ go through the u-boot.
301 if (spl_boot_device() == BOOT_DEVICE_MMC1)
304 /* break into full u-boot on 'c' */
305 if (serial_tstc() && serial_getc() == 'c')
309 ret = env_get_f("boot_os", s, sizeof(s));
310 if ((ret != -1) && (strcmp(s, "no") == 0))
314 * Check if SWUpdate recovery needs to be started
316 * recovery_status = NULL (not set - ret == -1) -> normal operation
318 * recovery_status = progress or
319 * recovery_status = failed or
320 * recovery_status = <any value> -> start SWUpdate
323 ret = env_get_f("recovery_status", s, sizeof(s));
329 #endif /* CONFIG_SPL_OS_BOOT */