board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <serial.h>
  10 #include <spl.h>
  11 #include <linux/libfdt.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/mx6-ddr.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include "asm/arch/crm_regs.h"
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include "asm/arch/iomux.h"
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/gpio.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <netdev.h>
  24 #include <bootcount.h>
  25 #include <watchdog.h>
  26 #include "common.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  31         .dram_sdclk_0 = 0x00000030,
  32         .dram_sdclk_1 = 0x00000030,
  33         .dram_cas = 0x00000030,
  34         .dram_ras = 0x00000030,
  35         .dram_reset = 0x00000030,
  36         .dram_sdcke0 = 0x00003000,
  37         .dram_sdcke1 = 0x00003000,
  38         .dram_sdba2 = 0x00000000,
  39         .dram_sdodt0 = 0x00000030,
  40         .dram_sdodt1 = 0x00000030,
  41
  42         .dram_sdqs0 = 0x00000030,
  43         .dram_sdqs1 = 0x00000030,
  44         .dram_sdqs2 = 0x00000030,
  45         .dram_sdqs3 = 0x00000030,
  46         .dram_sdqs4 = 0x00000030,
  47         .dram_sdqs5 = 0x00000030,
  48         .dram_sdqs6 = 0x00000030,
  49         .dram_sdqs7 = 0x00000030,
  50
  51         .dram_dqm0 = 0x00000030,
  52         .dram_dqm1 = 0x00000030,
  53         .dram_dqm2 = 0x00000030,
  54         .dram_dqm3 = 0x00000030,
  55         .dram_dqm4 = 0x00000030,
  56         .dram_dqm5 = 0x00000030,
  57         .dram_dqm6 = 0x00000030,
  58         .dram_dqm7 = 0x00000030,
  59 };
  60
  61 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  62         .grp_ddr_type = 0x000c0000,
  63         .grp_ddrmode_ctl = 0x00020000,
  64         .grp_ddrpke = 0x00000000,
  65         .grp_addds = 0x00000030,
  66         .grp_ctlds = 0x00000030,
  67         .grp_ddrmode = 0x00020000,
  68         .grp_b0ds = 0x00000030,
  69         .grp_b1ds = 0x00000030,
  70         .grp_b2ds = 0x00000030,
  71         .grp_b3ds = 0x00000030,
  72         .grp_b4ds = 0x00000030,
  73         .grp_b5ds = 0x00000030,
  74         .grp_b6ds = 0x00000030,
  75         .grp_b7ds = 0x00000030,
  76 };
  77
  78 /* 4x128Mx16.cfg */
  79 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  80         .p0_mpwldectrl0 = 0x002D0028,
  81         .p0_mpwldectrl1 = 0x0032002D,
  82         .p1_mpwldectrl0 = 0x00210036,
  83         .p1_mpwldectrl1 = 0x0019002E,
  84         .p0_mpdgctrl0 = 0x4349035C,
  85         .p0_mpdgctrl1 = 0x0348033D,
  86         .p1_mpdgctrl0 = 0x43550362,
  87         .p1_mpdgctrl1 = 0x03520316,
  88         .p0_mprddlctl = 0x41393940,
  89         .p1_mprddlctl = 0x3F3A3C47,
  90         .p0_mpwrdlctl = 0x413A423A,
  91         .p1_mpwrdlctl = 0x4042483E,
  92 };
  93
  94 /* MT41K128M16JT-125 (2Gb density) */
  95 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  96         .mem_speed = 1600,
  97         .density = 2,
  98         .width = 16,
  99         .banks = 8,
 100         .rowaddr = 14,
 101         .coladdr = 10,
 102         .pagesz = 2,
 103         .trcd = 1375,
 104         .trcmin = 4875,
 105         .trasmin = 3500,
 106 };
 107
 108 iomux_v3_cfg_t const uart_console_pads[] = {
 109         /* UART5 */
 110         MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 111         MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 112         MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 113         MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 114 };
 115
 116 void displ5_set_iomux_uart_spl(void)
 117 {
 118         SETUP_IOMUX_PADS(uart_console_pads);
 119 }
 120
 121 iomux_v3_cfg_t const misc_pads_spl[] = {
 122         /* Emergency recovery pin */
 123         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 124 };
 125
 126 void displ5_set_iomux_misc_spl(void)
 127 {
 128         SETUP_IOMUX_PADS(misc_pads_spl);
 129 }
 130
 131 #ifdef CONFIG_MXC_SPI
 132 iomux_v3_cfg_t const ecspi2_pads[] = {
 133         /* SPI2, NOR Flash nWP, CS0 */
 134         MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 135         MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 136         MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 137         MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 138         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
 139 };
 140
 141 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 142 {
 143         if (bus != 1 || cs != 0)
 144                 return -EINVAL;
 145
 146         return IMX_GPIO_NR(5, 29);
 147 }
 148
 149 void displ5_set_iomux_ecspi_spl(void)
 150 {
 151         SETUP_IOMUX_PADS(ecspi2_pads);
 152 }
 153
 154 #else
 155 void displ5_set_iomux_ecspi_spl(void) {}
 156 #endif
 157
 158 #ifdef CONFIG_FSL_ESDHC_IMX
 159 iomux_v3_cfg_t const usdhc4_pads[] = {
 160         MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171 };
 172
 173 void displ5_set_iomux_usdhc_spl(void)
 174 {
 175         SETUP_IOMUX_PADS(usdhc4_pads);
 176 }
 177
 178 #else
 179 void displ5_set_iomux_usdhc_spl(void) {}
 180 #endif
 181
 182 static void ccgr_init(void)
 183 {
 184         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 185
 186         writel(0x00C03F3F, &ccm->CCGR0);
 187         writel(0x0030FC3F, &ccm->CCGR1);
 188         writel(0x0FFFCFC0, &ccm->CCGR2);
 189         writel(0x3FF00000, &ccm->CCGR3);
 190         writel(0x00FFF300, &ccm->CCGR4);
 191         writel(0x0F0000C3, &ccm->CCGR5);
 192         writel(0x000003FF, &ccm->CCGR6);
 193 }
 194
 195 #ifdef CONFIG_MX6_DDRCAL
 196 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
 197 {
 198         struct mx6_mmdc_calibration calibration = {0};
 199
 200         mmdc_read_calibration(sysinfo, &calibration);
 201
 202         debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
 203         debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
 204         debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
 205         debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
 206         debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
 207         debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
 208         debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
 209         debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
 210         debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
 211         debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
 212         debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
 213         debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
 214 }
 215
 216 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 217 {
 218         int ret;
 219
 220         /* Perform DDR DRAM calibration */
 221         udelay(100);
 222         ret = mmdc_do_write_level_calibration(sysinfo);
 223         if (ret) {
 224                 printf("DDR: Write level calibration error [%d]\n", ret);
 225                 return;
 226         }
 227
 228         ret = mmdc_do_dqs_calibration(sysinfo);
 229         if (ret) {
 230                 printf("DDR: DQS calibration error [%d]\n", ret);
 231                 return;
 232         }
 233
 234         spl_dram_print_cal(sysinfo);
 235 }
 236 #endif /* CONFIG_MX6_DDRCAL */
 237
 238 static void spl_dram_init(void)
 239 {
 240         struct mx6_ddr_sysinfo sysinfo = {
 241                 /* width of data bus:0=16,1=32,2=64 */
 242                 .dsize = 2,
 243                 /* config for full 4GB range so that get_mem_size() works */
 244                 .cs_density = 32, /* 32Gb per CS */
 245                 /* single chip select */
 246                 .ncs = 1,
 247                 .cs1_mirror = 0,
 248                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 249                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 250                 .walat = 1,     /* Write additional latency */
 251                 .ralat = 5,     /* Read additional latency */
 252                 .mif3_mode = 3, /* Command prediction working mode */
 253                 .bi_on = 1,     /* Bank interleaving enabled */
 254                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 255                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 256                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 257                 .ddr_type = DDR_TYPE_DDR3,
 258                 .refsel = 1,    /* Refresh cycles at 32KHz */
 259                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 260         };
 261
 262         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 263         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 264
 265 #ifdef CONFIG_MX6_DDRCAL
 266         spl_dram_perform_cal(&sysinfo);
 267 #endif
 268 }
 269
 270 #ifdef CONFIG_SPL_SPI_SUPPORT
 271 static void displ5_init_ecspi(void)
 272 {
 273         displ5_set_iomux_ecspi_spl();
 274         enable_spi_clk(1, 1);
 275 }
 276 #else
 277 static inline void displ5_init_ecspi(void) { }
 278 #endif
 279
 280 #ifdef CONFIG_SPL_MMC_SUPPORT
 281 static struct fsl_esdhc_cfg usdhc_cfg = {
 282         .esdhc_base = USDHC4_BASE_ADDR,
 283         .max_bus_width = 8,
 284 };
 285
 286 int board_mmc_init(bd_t *bd)
 287 {
 288         displ5_set_iomux_usdhc_spl();
 289
 290         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 291         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 292
 293         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 294 }
 295 #endif
 296
 297 void board_init_f(ulong dummy)
 298 {
 299         ccgr_init();
 300
 301         arch_cpu_init();
 302
 303         gpr_init();
 304
 305         /* setup GP timer */
 306         timer_init();
 307
 308         displ5_set_iomux_uart_spl();
 309
 310         /* UART clocks enabled and gd valid - init serial console */
 311         preloader_console_init();
 312
 313         displ5_init_ecspi();
 314
 315         /* DDR initialization */
 316         spl_dram_init();
 317
 318         /* Clear the BSS. */
 319         memset(__bss_start, 0, __bss_end - __bss_start);
 320
 321         displ5_set_iomux_misc_spl();
 322
 323         /* Initialize and reset WDT in SPL */
 324         hw_watchdog_init();
 325         WATCHDOG_RESET();
 326
 327         /* load/boot image from boot device */
 328         board_init_r(NULL, 0);
 329 }
 330
 331 #define EM_PAD IMX_GPIO_NR(3, 29)
 332 int board_check_emergency_pad(void)
 333 {
 334         int ret;
 335
 336         ret = gpio_direction_input(EM_PAD);
 337         if (ret)
 338                 return ret;
 339
 340         return !gpio_get_value(EM_PAD);
 341 }
 342
 343 void board_boot_order(u32 *spl_boot_list)
 344 {
 345         /* Default boot sequence SPI -> MMC */
 346         spl_boot_list[0] = spl_boot_device();
 347         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 348         spl_boot_list[2] = BOOT_DEVICE_UART;
 349         spl_boot_list[3] = BOOT_DEVICE_NONE;
 350
 351         /*
 352          * In case of emergency PAD pressed, we always boot
 353          * to proper u-boot and perform recovery tasks there.
 354          */
 355         if (board_check_emergency_pad())
 356                 return;
 357
 358 #ifdef CONFIG_SPL_ENV_SUPPORT
 359         /* 'fastboot' */
 360         const char *s;
 361
 362         if (env_init() || env_load())
 363                 return;
 364
 365         s = env_get("BOOT_FROM");
 366         if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
 367                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 368                 spl_boot_list[1] = spl_boot_device();
 369         }
 370 #endif
 371 }
 372
 373 void reset_cpu(ulong addr) {}
 374
 375 #ifdef CONFIG_SPL_LOAD_FIT
 376 int board_fit_config_name_match(const char *name)
 377 {
 378         return 0;
 379 }
 380 #endif
 381
 382 #ifdef CONFIG_SPL_OS_BOOT
 383 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 384 int spl_start_uboot(void)
 385 {
 386         /* break into full u-boot on 'c' */
 387         if (serial_tstc() && serial_getc() == 'c')
 388                 return 1;
 389
 390 #ifdef CONFIG_SPL_ENV_SUPPORT
 391         if (env_get_yesno("boot_os") != 1)
 392                 return 1;
 393 #endif
 394         return 0;
 395 }
 396 #endif