3 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/sama5_sfr.h>
9 #include <asm/arch/sama5d3_smc.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_pmc.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/gpio.h>
14 #include <asm/arch/clk.h>
19 #include <asm/arch/atmel_mpddrc.h>
20 #include <asm/arch/at91_wdt.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 /* ------------------------------------------------------------------------- */
26 * Miscelaneous platform dependent initialisations
29 void wb50n_nand_hw_init(void)
31 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
33 at91_periph_clk_enable(ATMEL_ID_SMC);
35 /* Configure SMC CS3 for NAND/SmartMedia */
36 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
37 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
39 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
40 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
42 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
44 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
45 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
46 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
47 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
48 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
49 AT91_SMC_MODE_EXNW_DISABLE |
51 AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
53 /* Disable Flash Write Protect Line */
54 at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
57 int board_early_init_f(void)
59 at91_periph_clk_enable(ATMEL_ID_PIOA);
60 at91_periph_clk_enable(ATMEL_ID_PIOB);
61 at91_periph_clk_enable(ATMEL_ID_PIOC);
62 at91_periph_clk_enable(ATMEL_ID_PIOD);
63 at91_periph_clk_enable(ATMEL_ID_PIOE);
65 at91_seriald_hw_init();
72 /* adress of boot parameters */
73 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
84 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
85 CONFIG_SYS_SDRAM_SIZE);
89 int board_phy_config(struct phy_device *phydev)
92 ksz9021_phy_extended_write(phydev,
93 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
95 ksz9021_phy_extended_write(phydev,
96 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
97 /* rx/tx clock delay */
98 ksz9021_phy_extended_write(phydev,
99 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
104 int board_eth_init(bd_t *bis)
108 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
113 #ifdef CONFIG_BOARD_LATE_INIT
114 #include <linux/ctype.h>
115 int board_late_init(void)
117 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
118 const char *LAIRD_NAME = "lrd_name";
121 strcpy(name, get_cpu_name());
122 for (p = name; *p != '\0'; *p = tolower(*p), p++)
124 strcat(name, "-wb50n");
125 env_set(LAIRD_NAME, name);
134 #ifdef CONFIG_SPL_BUILD
135 void spl_board_init(void)
137 wb50n_nand_hw_init();
140 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
142 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
144 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
145 ATMEL_MPDDRC_CR_NR_ROW_13 |
146 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
147 ATMEL_MPDDRC_CR_NDQS_DISABLED |
148 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
149 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
153 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
154 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
155 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
156 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
157 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
158 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
159 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
160 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
162 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
163 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
164 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
165 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
167 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
168 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
169 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
170 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
171 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
176 struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
177 struct atmel_mpddrc_config ddr2;
181 writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN,
184 /* enable MPDDR clock */
185 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
186 at91_system_clk_enable(AT91_PMC_DDR);
188 /* DDRAM2 Controller initialize */
189 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
192 void at91_pmc_init(void)
196 tmp = AT91_PMC_PLLAR_29 |
197 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
198 AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
201 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
203 tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;