2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifdef CONFIG_KUP4K_LOGO
34 volatile unsigned char *VmemAddr;
35 volatile unsigned char *RegAddr;
38 /* ------------------------------------------------------------------------- */
41 static long int dram_size (long int, long int *, long int);
44 #ifdef CONFIG_KUP4K_LOGO
45 void lcd_logo(bd_t *bd);
48 /* ------------------------------------------------------------------------- */
50 #define _NOT_USED_ 0xFFFFFFFF
52 const uint sdram_table[] =
55 * Single Read. (Offset 0 in UPMA RAM)
61 0x1FF77C47, /* last */
64 * SDRAM Initialization (offset 5 in UPMA RAM)
66 * This is no UPM entry point. The following definition uses
67 * the remaining space to establish an initialization
68 * sequence, which is executed by a RUN command.
73 0x1FB57C35, /* last */
76 * Burst Read. (Offset 8 in UPMA RAM)
85 0x1FF77C47, /* last */
86 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
87 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 * Single Write. (Offset 18 in UPMA RAM)
95 0x1FF77C47, /* last */
96 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
99 * Burst Write. (Offset 20 in UPMA RAM)
107 0x1FF77C47, /* last */
109 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
110 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 * Refresh (Offset 30 in UPMA RAM)
120 0xFFFFFC07, /* last */
121 _NOT_USED_, _NOT_USED_,
122 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
125 * Exception. (Offset 3c in UPMA RAM)
127 0x7FFFFC07, /* last */
128 _NOT_USED_, _NOT_USED_, _NOT_USED_,
131 /* ------------------------------------------------------------------------- */
135 * Check Board Identity:
138 int checkboard (void)
141 printf ("### No HW ID - assuming KUP4K-Color\n");
145 /* ------------------------------------------------------------------------- */
147 long int initdram (int board_type)
149 volatile immap_t *immap = (immap_t *)CFG_IMMR;
150 volatile memctl8xx_t *memctl = &immap->im_memctl;
151 long int size_b0 = 0;
152 long int size_b1 = 0;
153 long int size_b2 = 0;
155 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
158 * Preliminary prescaler for refresh (depends on number of
159 * banks): This value is selected for four cycles every 62.4 us
160 * with two SDRAM banks or four cycles every 31.2 us with one
161 * bank. It will be adjusted after memory sizing.
163 memctl->memc_mptpr = CFG_MPTPR;
165 memctl->memc_mar = 0x00000088;
168 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
169 * preliminary addresses - these have to be modified after the
170 * SDRAM size has been determined.
172 /* memctl->memc_or1 = CFG_OR1_PRELIM; */
173 /* memctl->memc_br1 = CFG_BR1_PRELIM; */
175 /* memctl->memc_or2 = CFG_OR2_PRELIM; */
176 /* memctl->memc_br2 = CFG_BR2_PRELIM; */
179 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
183 /* perform SDRAM initializsation sequence */
185 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
187 memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
189 memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
192 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
194 memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
196 memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
199 memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
201 memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
203 memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
207 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
211 size_b0 = 0x00800000;
212 size_b1 = 0x00800000;
213 size_b2 = 0x00800000;
216 memctl->memc_mptpr = CFG_MPTPR;
219 memctl->memc_or1 = 0xFF800A00;
220 memctl->memc_br1 = 0x00000081;
222 memctl->memc_or2 = 0xFF000A00;
223 memctl->memc_br2 = 0x00800081;
225 memctl->memc_or3 = 0xFE000A00;
226 memctl->memc_br3 = 0x01000081;
231 return (size_b0 + size_b1 + size_b2);
234 /* ------------------------------------------------------------------------- */
237 * Check memory range for valid RAM. A simple memory test determines
238 * the actually available RAM size between addresses `base' and
239 * `base + maxsize'. Some (not all) hardware errors are detected:
240 * - short between address lines
241 * - short between data lines
244 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
246 volatile immap_t *immap = (immap_t *)CFG_IMMR;
247 volatile memctl8xx_t *memctl = &immap->im_memctl;
248 volatile long int *addr;
250 ulong save[32]; /* to make test non-destructive */
253 memctl->memc_mamr = mamr_value;
255 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
256 addr = base + cnt; /* pointer arith! */
262 /* write 0 to base address */
267 /* check at base address */
268 if ((val = *addr) != 0) {
273 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
274 addr = base + cnt; /* pointer arith! */
280 return (cnt * sizeof(long));
287 int misc_init_r (void)
289 DECLARE_GLOBAL_DATA_PTR;
291 #ifdef CONFIG_STATUS_LED
292 volatile immap_t *immap = (immap_t *)CFG_IMMR;
294 #ifdef CONFIG_KUP4K_LOGO
299 #endif /* CONFIG_KUP4K_LOGO */
300 #ifdef CONFIG_IDE_LED
301 /* Configure PA8 as output port */
302 immap->im_ioport.iop_padir |= 0x80;
303 immap->im_ioport.iop_paodr |= 0x80;
304 immap->im_ioport.iop_papar &= ~0x80;
305 immap->im_ioport.iop_padat |= 0x80; /* turn it off */
310 #ifdef CONFIG_KUP4K_LOGO
311 void lcd_logo(bd_t *bd){
313 FB_INFO_S1D13xxx fb_info;
316 volatile immap_t *immr = (immap_t *)CFG_IMMR;
317 volatile memctl8xx_t *memctl;
321 int r = 8, g = 8, b = 4;
324 /*----------------------------------------------------------------------------- */
326 /* Initialize the chip and the frame buffer driver. */
328 /*----------------------------------------------------------------------------- */
329 memctl = &immr->im_memctl;
330 /* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
331 /* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
333 memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
334 memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
340 fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
341 fb_info.RegAddr = (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
343 if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
345 printf("Warning:LCD Controller S1D13706 not found\n");
349 /* init controller */
350 for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
352 s1dReg = aS1DRegs[i].Index;
353 s1dValue = aS1DRegs[i].Value;
354 /* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
355 ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
360 switch(bd->bi_busfreq){
363 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
364 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
367 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
368 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
372 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
373 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
376 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
377 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
380 printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
382 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
383 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
386 ((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
388 switch(bd->bi_busfreq){
391 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
392 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
395 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
396 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
400 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
401 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
404 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
405 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
408 printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
410 ((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
411 ((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
417 /* create and set colormap */
422 r1=(rs * ((i / (g * b)) % r)) * 255;
423 g1=(gs * ((i / b) % g)) * 255;
424 b1=(bs * ((i) % b)) * 255;
425 /* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
426 S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
430 fb = (char *) (fb_info.VmemAddr);
431 memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
433 #endif /* CONFIG_KUP4K_LOGO */
435 #ifdef CONFIG_IDE_LED
436 void ide_led (uchar led, uchar status)
438 volatile immap_t *immap = (immap_t *)CFG_IMMR;
439 /* We have one led for both pcmcia slots */
440 if (status) { /* led on */
441 immap->im_ioport.iop_padat &= ~0x80;
443 immap->im_ioport.iop_padat |= 0x80;