2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include "../common/kup.h"
33 static unsigned char swapbyte(unsigned char c);
34 static int read_diag(void);
36 DECLARE_GLOBAL_DATA_PTR;
38 /* ----------------------------------------------------------------------- */
40 #define _NOT_USED_ 0xFFFFFFFF
42 const uint sdram_table[] = {
44 * Single Read. (Offset 0 in UPMA RAM)
46 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
47 0x1FF77C47, /* last */
50 * SDRAM Initialization (offset 5 in UPMA RAM)
52 * This is no UPM entry point. The following definition uses
53 * the remaining space to establish an initialization
54 * sequence, which is executed by a RUN command.
57 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
60 * Burst Read. (Offset 8 in UPMA RAM)
62 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
63 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 * Single Write. (Offset 18 in UPMA RAM)
70 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 * Burst Write. (Offset 20 in UPMA RAM)
76 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
77 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 * Refresh (Offset 30 in UPMA RAM)
85 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
86 0xFFFFFC84, 0xFFFFFC07, /* last */
87 _NOT_USED_, _NOT_USED_,
88 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
91 * Exception. (Offset 3c in UPMA RAM)
93 0x7FFFFC07, /* last */
94 _NOT_USED_, _NOT_USED_, _NOT_USED_,
97 /* ----------------------------------------------------------------------- */
100 * Check Board Identity:
105 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
106 uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
109 * Init ChipSelect #4 (CAN + HW-Latch)
111 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
112 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
115 * Init ChipSelect #5 (S1D13768)
117 out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
118 out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
120 tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
121 rev = (tmp & 0xF8) >> 3;
124 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
127 gd->flags &= ~GD_FLG_SILENT;
129 printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
131 * TI Application report: Before using the IO as an input,
132 * a high must be written to the IO first
135 i2c_write(0x21, 0, 0 , &pcf, 1);
136 if (i2c_read(0x21, 0, 0, &pcf, 1)) {
139 ak_rev = (pcf & 0xF8) >> 3;
140 ak_mod = (pcf & 0x07);
141 printf("%d.%d\n", ak_rev, ak_mod);
146 /* ----------------------------------------------------------------------- */
149 phys_size_t initdram(int board_type)
151 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
152 volatile memctl8xx_t *memctl = &immap->im_memctl;
154 uchar *latch,rev,mod,tmp;
157 * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
158 * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB
160 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
161 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
163 latch = (uchar *)0x90000200;
164 tmp = swapbyte(*latch);
165 rev = (tmp & 0xF8) >> 3;
168 upmconfig(UPMA, (uint *) sdram_table,
169 sizeof (sdram_table) / sizeof (uint));
171 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
173 out_be32(&memctl->memc_mar, 0x00000088);
176 out_be32(&memctl->memc_mamr,
177 CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
179 out_be32(&memctl->memc_mamr,
180 CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
185 /* perform SDRAM initializsation sequence */
188 out_be32(&memctl->memc_mcr, 0x80002105);
190 out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
192 out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
196 out_be32(&memctl->memc_mcr, 0x80004105);
198 out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
200 out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
204 out_be32(&memctl->memc_mcr, 0x80006105);
206 out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
208 out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
211 setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
214 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
217 size = 32 * 3 * 1024 * 1024;
218 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
219 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
220 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
221 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
222 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
223 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
225 size = 16 * 3 * 1024 * 1024;
226 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
227 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
228 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
229 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
230 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
231 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
236 /* ----------------------------------------------------------------------- */
239 int misc_init_r(void)
241 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
243 #ifdef CONFIG_IDE_LED
244 /* Configure PA8 as output port */
245 setbits_be16(&immap->im_ioport.iop_padir, PA_8);
246 setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
247 clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
248 setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
250 load_sernum_ethaddr();
257 static int read_diag(void)
260 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
262 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
263 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
264 setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
265 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
266 setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
268 if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
269 clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
271 if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
278 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
282 static unsigned char swapbyte(unsigned char c)
284 unsigned char result = 0;
287 for(i = 0; i < 8; ++i) {
288 result = result << 1;