2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include "../common/kup.h"
28 #ifdef CONFIG_KUP4K_LOGO
34 # define debugk(fmt,args...) printf(fmt ,##args)
36 # define debugk(fmt,args...)
40 volatile unsigned char *VmemAddr;
41 volatile unsigned char *RegAddr;
45 /* ------------------------------------------------------------------------- */
48 static long int dram_size (long int, long int *, long int);
51 #ifdef CONFIG_KUP4K_LOGO
52 void lcd_logo(bd_t *bd);
56 /* ------------------------------------------------------------------------- */
58 #define _NOT_USED_ 0xFFFFFFFF
60 const uint sdram_table[] = {
62 * Single Read. (Offset 0 in UPMA RAM)
64 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
65 0x1FF77C47, /* last */
68 * SDRAM Initialization (offset 5 in UPMA RAM)
70 * This is no UPM entry point. The following definition uses
71 * the remaining space to establish an initialization
72 * sequence, which is executed by a RUN command.
75 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
78 * Burst Read. (Offset 8 in UPMA RAM)
80 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
81 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
86 * Single Write. (Offset 18 in UPMA RAM)
88 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
92 * Burst Write. (Offset 20 in UPMA RAM)
94 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
95 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
97 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
98 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
101 * Refresh (Offset 30 in UPMA RAM)
103 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
104 0xFFFFFC84, 0xFFFFFC07, /* last */
105 _NOT_USED_, _NOT_USED_,
106 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
109 * Exception. (Offset 3c in UPMA RAM)
111 0x7FFFFC07, /* last */
112 _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 /* ------------------------------------------------------------------------- */
119 * Check Board Identity:
122 int checkboard (void)
124 volatile immap_t *immap = (immap_t *) CFG_IMMR;
125 uchar *latch,rev,mod;
128 * Init ChipSelect #4 (CAN + HW-Latch)
130 immap->im_memctl.memc_or4 = 0xFFFF8926;
131 immap->im_memctl.memc_br4 = 0x90000401;
133 latch=(uchar *)0x90000200;
134 rev = (*latch & 0xF8) >> 3;
136 printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
140 /* ------------------------------------------------------------------------- */
142 long int initdram (int board_type)
144 volatile immap_t *immap = (immap_t *) CFG_IMMR;
145 volatile memctl8xx_t *memctl = &immap->im_memctl;
146 long int size_b0 = 0;
147 long int size_b1 = 0;
148 long int size_b2 = 0;
150 upmconfig (UPMA, (uint *) sdram_table,
151 sizeof (sdram_table) / sizeof (uint));
154 * Preliminary prescaler for refresh (depends on number of
155 * banks): This value is selected for four cycles every 62.4 us
156 * with two SDRAM banks or four cycles every 31.2 us with one
157 * bank. It will be adjusted after memory sizing.
159 memctl->memc_mptpr = CFG_MPTPR;
161 memctl->memc_mar = 0x00000088;
164 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
165 * preliminary addresses - these have to be modified after the
166 * SDRAM size has been determined.
168 /* memctl->memc_or1 = CFG_OR1_PRELIM; */
169 /* memctl->memc_br1 = CFG_BR1_PRELIM; */
171 /* memctl->memc_or2 = CFG_OR2_PRELIM; */
172 /* memctl->memc_br2 = CFG_BR2_PRELIM; */
175 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
179 /* perform SDRAM initializsation sequence */
181 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
183 memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
185 memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
188 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
190 memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
192 memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
195 memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
197 memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
199 memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
202 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
206 size_b0 = 0x00800000;
207 size_b1 = 0x00800000;
208 size_b2 = 0x00800000;
209 memctl->memc_mptpr = CFG_MPTPR;
211 memctl->memc_or1 = 0xFF800A00;
212 memctl->memc_br1 = 0x00000081;
213 memctl->memc_or2 = 0xFF000A00;
214 memctl->memc_br2 = 0x00800081;
215 memctl->memc_or3 = 0xFE000A00;
216 memctl->memc_br3 = 0x01000081;
217 #else /* 3 x 16 MB */
218 size_b0 = 0x01000000;
219 size_b1 = 0x01000000;
220 size_b2 = 0x01000000;
221 memctl->memc_mptpr = CFG_MPTPR;
223 memctl->memc_or1 = 0xFF000A00;
224 memctl->memc_br1 = 0x00000081;
225 memctl->memc_or2 = 0xFE000A00;
226 memctl->memc_br2 = 0x01000081;
227 memctl->memc_or3 = 0xFC000A00;
228 memctl->memc_br3 = 0x02000081;
233 return (size_b0 + size_b1 + size_b2);
236 /* ------------------------------------------------------------------------- */
239 * Check memory range for valid RAM. A simple memory test determines
240 * the actually available RAM size between addresses `base' and
241 * `base + maxsize'. Some (not all) hardware errors are detected:
242 * - short between address lines
243 * - short between data lines
246 static long int dram_size (long int mamr_value, long int *base,
249 volatile immap_t *immap = (immap_t *) CFG_IMMR;
250 volatile memctl8xx_t *memctl = &immap->im_memctl;
251 volatile long int *addr;
253 ulong save[32]; /* to make test non-destructive */
256 memctl->memc_mamr = mamr_value;
258 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
259 addr = base + cnt; /* pointer arith! */
265 /* write 0 to base address */
270 /* check at base address */
271 if ((val = *addr) != 0) {
276 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
277 addr = base + cnt; /* pointer arith! */
283 return (cnt * sizeof (long));
290 int misc_init_r (void)
292 DECLARE_GLOBAL_DATA_PTR;
294 #ifdef CONFIG_STATUS_LED
295 volatile immap_t *immap = (immap_t *) CFG_IMMR;
297 #ifdef CONFIG_KUP4K_LOGO
301 #endif /* CONFIG_KUP4K_LOGO */
302 #ifdef CONFIG_IDE_LED
303 /* Configure PA8 as output port */
304 immap->im_ioport.iop_padir |= 0x80;
305 immap->im_ioport.iop_paodr |= 0x80;
306 immap->im_ioport.iop_papar &= ~0x80;
307 immap->im_ioport.iop_padat |= 0x80; /* turn it off */
314 #ifdef CONFIG_KUP4K_LOGO
317 void lcd_logo (bd_t * bd)
319 FB_INFO_S1D13xxx fb_info;
322 volatile immap_t *immr = (immap_t *) CFG_IMMR;
323 volatile memctl8xx_t *memctl;
327 int r = 8, g = 8, b = 4;
330 char tmp[64]; /* long enough for environment variables */
333 immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
334 immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
335 immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */
336 immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
338 /*----------------------------------------------------------------------------- */
339 /* Initialize the chip and the frame buffer driver. */
340 /*----------------------------------------------------------------------------- */
341 memctl = &immr->im_memctl;
345 * Init ChipSelect #5 (S1D13768)
347 memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */
348 memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
351 fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
352 fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
354 if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
355 || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
356 printf ("Warning:LCD Controller S1D13706 not found\n");
357 setenv ("lcd", "none");
362 for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
363 s1dReg = aS1DRegs_prelimn[i].Index;
364 s1dValue = aS1DRegs_prelimn[i].Value;
365 debugk ("s13768 reg: %02x value: %02x\n",
366 aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
367 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
372 n = getenv_r ("lcd", tmp, sizeof (tmp));
374 if (!strcmp ("tft", tmp))
380 if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
386 debugk ("Port=0x%02x -> TFT=%d\n", tft,
387 ((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
389 /* init controller */
391 for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
392 s1dReg = aS1DRegs_stn[i].Index;
393 s1dValue = aS1DRegs_stn[i].Value;
394 debugk ("s13768 reg: %02x value: %02x\n",
395 aS1DRegs_stn[i].Index,
396 aS1DRegs_stn[i].Value);
397 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
400 n = getenv_r ("contrast", tmp, sizeof (tmp));
401 ((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
402 (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
403 switch (bd->bi_busfreq) {
405 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
406 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
409 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
410 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
413 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
415 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
416 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
419 /* setenv("lcd","stn"); */
421 for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
422 s1dReg = aS1DRegs_tft[i].Index;
423 s1dValue = aS1DRegs_tft[i].Value;
424 debugk ("s13768 reg: %02x value: %02x\n",
425 aS1DRegs_tft[i].Index,
426 aS1DRegs_tft[i].Value);
427 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
431 switch (bd->bi_busfreq) {
433 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
435 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
436 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
439 /* setenv("lcd","tft"); */
442 /* create and set colormap */
446 for (i = 0; i < 256; i++) {
447 r1 = (rs * ((i / (g * b)) % r)) * 255;
448 g1 = (gs * ((i / b) % g)) * 255;
449 b1 = (bs * ((i) % b)) * 255;
450 debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
451 S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
456 fb = (uchar *) (fb_info.VmemAddr);
457 memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
459 #endif /* CONFIG_KUP4K_LOGO */