1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
4 * based on board/solidrun/clearfog/clearfog.c
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include <../serdes/a38x/high_speed_env_spec.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define ETH_PHY_CTRL_REG 0
21 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
22 #define ETH_PHY_CTRL_POWER_DOWN_MASK BIT(ETH_PHY_CTRL_POWER_DOWN_BIT)
25 * Those values and defines are taken from the Marvell U-Boot version
26 * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
28 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
29 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
31 #define BOARD_GPP_OUT_VAL_LOW 0x0
32 #define BOARD_GPP_OUT_VAL_MID 0x0
33 #define BOARD_GPP_POL_LOW 0x0
34 #define BOARD_GPP_POL_MID 0x0
36 /* IO expander on Marvell GP board includes e.g. fan enabling */
37 struct marvell_io_exp {
42 static struct marvell_io_exp io_exp[] = {
44 {2, 0x46}, /* Assert reset signals and enable USB3 current limiter */
48 static struct serdes_map board_serdes_map[] = {
49 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
50 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
51 {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
52 {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
53 {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
54 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
57 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
59 *serdes_map_array = board_serdes_map;
60 *count = ARRAY_SIZE(board_serdes_map);
65 * Define the DDR layout / topology here in the board file. This will
66 * be used by the DDR3 init code in the SPL U-Boot version to configure
67 * the DDR3 controller.
69 static struct mv_ddr_topology_map board_topology_map = {
71 0x1, /* active interfaces */
72 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
78 SPEED_BIN_DDR_1600K, /* speed_bin */
79 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
80 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
81 MV_DDR_FREQ_800, /* frequency */
82 0, 0, /* cas_wl cas_l */
83 MV_DDR_TEMP_LOW, /* temperature */
84 MV_DDR_TIM_DEFAULT} }, /* timing */
85 BUS_MASK_32BIT_ECC, /* Busses mask */
86 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
87 { {0} }, /* raw spd data */
88 {0} /* timing parameters */
91 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
93 /* Return the board topology as defined in the board code */
94 return &board_topology_map;
97 int board_early_init_f(void)
100 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
101 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
102 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
103 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
104 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
105 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
106 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
107 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
109 /* Set GPP Out value */
110 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
111 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
113 /* Set GPP Polarity */
114 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
115 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
117 /* Set GPP Out Enable */
118 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
119 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
128 /* Address of boot parameters */
129 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
131 /* Init I2C IO expanders */
132 for (i = 0; i < ARRAY_SIZE(io_exp); i++) {
136 ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev);
138 printf("Cannot find I2C: %d\n", ret);
142 ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1);
144 printf("Failed to set IO expander via I2C\n");
154 puts("Board: Helios4\n");
159 int board_eth_init(bd_t *bis)
161 cpu_eth_init(bis); /* Built in controller(s) come first */
162 return pci_eth_init(bis);