board/keymile/kmp204x/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Keymile AG
   4  * Valentin Longchamp <valentin.longchamp@keymile.com>
   5  *
   6  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  */
  11
  12 #include <common.h>
  13 #include <asm/mmu.h>
  14
  15 struct fsl_e_tlb_entry tlb_table[] = {
  16         /* TLB 0 - for temp stack in cache */
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  18                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  19                       MAS3_SW|MAS3_SR, 0,
  20                       0, 0, BOOKE_PAGESZ_4K, 0),
  21         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  22                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  23                       MAS3_SW|MAS3_SR, 0,
  24                       0, 0, BOOKE_PAGESZ_4K, 0),
  25         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  26                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  27                       MAS3_SW|MAS3_SR, 0,
  28                       0, 0, BOOKE_PAGESZ_4K, 0),
  29         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  30                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  31                       MAS3_SW|MAS3_SR, 0,
  32                       0, 0, BOOKE_PAGESZ_4K, 0),
  33         /* TLB 1 */
  34         /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  35          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  36          */
  37         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  38                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  39                       0, 0, BOOKE_PAGESZ_1M, 1),
  40
  41         /* *I*G* - CCSRBAR */
  42         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  43                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44                       0, 1, BOOKE_PAGESZ_16M, 1),
  45         /* QRIO */
  46         SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
  47                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48                       0, 2, BOOKE_PAGESZ_64K, 1),
  49         /* *I*G* - PCI1 */
  50         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  51                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52                       0, 3, BOOKE_PAGESZ_512M, 1),
  53         /* *I*G* - PCI3 */
  54         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  55                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                       0, 4, BOOKE_PAGESZ_512M, 1),
  57         /* *I*G* - PCI1&3 I/O */
  58         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  59                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60                       0, 6, BOOKE_PAGESZ_128K, 1),
  61 #ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
  62         /* LBAPP1 */
  63         SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
  64                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65                       0, 7, BOOKE_PAGESZ_256M, 1),
  66 #endif
  67 #ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
  68         /* LBAPP2 */
  69         SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
  70                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                       0, 8, BOOKE_PAGESZ_256M, 1),
  72 #endif
  73         /* Bman/Qman */
  74 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  75         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  76                       MAS3_SW|MAS3_SR, 0,
  77                       0, 9, BOOKE_PAGESZ_1M, 1),
  78         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  79                       CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  80                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  81                       0, 10, BOOKE_PAGESZ_1M, 1),
  82 #endif
  83 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  84         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  85                       MAS3_SW|MAS3_SR, 0,
  86                       0, 11, BOOKE_PAGESZ_1M, 1),
  87         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  88                       CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  89                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  90                       0, 12, BOOKE_PAGESZ_1M, 1),
  91 #endif
  92 #ifdef CONFIG_SYS_DCSRBAR_PHYS
  93         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  94                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  95                       0, 13, BOOKE_PAGESZ_4M, 1),
  96 #endif
  97 #ifdef CONFIG_SYS_NAND_BASE
  98         /*
  99          * *I*G - NAND
 100          * entry 14 and 15 has been used hard coded, they will be disabled
 101          * in cpu_init_f, so we use entry 16 for nand.
 102          */
 103         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 104                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 105                       0, 16, BOOKE_PAGESZ_32K, 1),
 106 #endif
 107 };
 108
 109 int num_tlb_entries = ARRAY_SIZE(tlb_table);