1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/soc.h>
26 #include <asm/arch/mpp.h>
28 #include "../common/common.h"
30 DECLARE_GLOBAL_DATA_PTR;
33 * BOCO FPGA definitions
36 #define REG_CTRL_H 0x02
37 #define MASK_WRL_UNITRUN 0x01
38 #define MASK_RBX_PGY_PRESENT 0x40
39 #define REG_IRQ_CIRQ2 0x2d
40 #define MASK_RBI_DEFECT_16 0x01
43 * PHY registers definitions
45 #define PHY_MARVELL_OUI 0x5043
46 #define PHY_MARVELL_88E1118_MODEL 0x0022
47 #define PHY_MARVELL_88E1118R_MODEL 0x0024
49 #define PHY_MARVELL_PAGE_REG 0x0016
50 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
52 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
53 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
55 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
57 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
58 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
60 /* I/O pin to erase flash RGPP09 = MPP43 */
61 #define KM_FLASH_ERASE_ENABLE 43
63 /* Multi-Purpose Pins Functionality configuration */
64 static const u32 kwmpp_config[] = {
73 #if defined(CONFIG_SYS_I2C_SOFT)
79 MPP12_GPO, /* Reserved */
82 MPP15_GPIO, /* Not used */
83 MPP16_GPIO, /* Not used */
84 MPP17_GPIO, /* Reserved */
101 MPP34_GPIO, /* CDL1 (input) */
102 MPP35_GPIO, /* CDL2 (input) */
103 MPP36_GPIO, /* MAIN_IRQ (input) */
104 MPP37_GPIO, /* BOARD_LED */
105 MPP38_GPIO, /* Piggy3 LED[1] */
106 MPP39_GPIO, /* Piggy3 LED[2] */
107 MPP40_GPIO, /* Piggy3 LED[3] */
108 MPP41_GPIO, /* Piggy3 LED[4] */
109 MPP42_GPIO, /* Piggy3 LED[5] */
110 MPP43_GPIO, /* Piggy3 LED[6] */
111 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
112 MPP45_GPIO, /* Piggy3 LED[8] */
113 MPP46_GPIO, /* Reserved */
114 MPP47_GPIO, /* Reserved */
115 MPP48_GPIO, /* Reserved */
116 MPP49_GPIO, /* SW_INTOUTn */
120 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
122 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
124 * All boards with PIGGY4 connected via a simple switch have ethernet always
127 int ethernet_present(void)
132 int ethernet_present(void)
137 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
138 printf("%s: Error reading Boco\n", __func__);
141 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
148 static int initialize_unit_leds(void)
151 * Init the unit LEDs per default they all are
152 * ok apart from bootstat
156 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
157 printf("%s: Error reading Boco\n", __func__);
160 buf |= MASK_WRL_UNITRUN;
161 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
162 printf("%s: Error writing Boco\n", __func__);
168 static void set_bootcount_addr(void)
171 unsigned int bootcountaddr;
172 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
173 sprintf((char *)buf, "0x%x", bootcountaddr);
174 env_set("bootcountaddr", (char *)buf);
177 int misc_init_r(void)
179 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
180 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
182 initialize_unit_leds();
184 set_bootcount_addr();
188 int board_early_init_f(void)
190 #if defined(CONFIG_SYS_I2C_SOFT)
193 /* set the 2 bitbang i2c pins as output gpios */
194 tmp = readl(MVEBU_GPIO0_BASE + 4);
195 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
197 /* adjust SDRAM size for bank 0 */
198 mvebu_sdram_size_adjust(0);
199 kirkwood_mpp_conf(kwmpp_config, NULL);
205 /* address of boot parameters */
206 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
209 * The KM_FLASH_GPIO_PIN switches between using a
210 * NAND or a SPI FLASH. Set this pin on start
213 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
214 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
216 #if defined(CONFIG_SYS_I2C_SOFT)
218 * Reinit the GPIO for I2C Bitbang driver so that the now
219 * available gpio framework is consistent. The calls to
220 * direction output in are not necessary, they are already done in
223 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
224 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
227 #if defined(CONFIG_SYS_EEPROM_WREN)
228 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
229 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
232 #if defined(CONFIG_KM_FPGA_CONFIG)
233 trigger_fpga_config();
239 int board_late_init(void)
241 #if defined(CONFIG_KM_COGE5UN)
242 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
244 /* if pin 1 do full erase */
245 if (dip_switch != 0) {
246 /* start bootloader */
247 puts("DIP: Enabled\n");
248 env_set("actual_bank", "0");
252 #if defined(CONFIG_KM_FPGA_CONFIG)
253 wait_for_fpga_config();
255 toggle_eeprom_spi_bus();
260 static const u32 spi_mpp_config[] = {
267 static u32 spi_mpp_backup[4];
269 int mvebu_board_spi_claim_bus(struct udevice *dev)
271 spi_mpp_backup[3] = 0;
273 /* set new spi mpp config and save current one */
274 kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
276 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
281 int mvebu_board_spi_release_bus(struct udevice *dev)
283 /* restore saved mpp config */
284 kirkwood_mpp_conf(spi_mpp_backup, NULL);
286 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
291 #if (defined(CONFIG_KM_PIGGY4_88E6061))
293 #define PHY_LED_SEL_REG 0x18
294 #define PHY_LED0_LINK (0x5)
295 #define PHY_LED1_ACT (0x8<<4)
296 #define PHY_LED2_INT (0xe<<8)
297 #define PHY_SPEC_CTRL_REG 0x1c
298 #define PHY_RGMII_CLK_STABLE (0x1<<10)
299 #define PHY_CLSA (0x1<<1)
301 /* Configure and enable MV88E3018 PHY */
304 char *name = "egiga0";
307 if (miiphy_set_current_dev(name))
310 /* RGMII clk transition on data stable */
311 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
312 printf("Error reading PHY spec ctrl reg\n");
313 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
314 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
315 printf("Error writing PHY spec ctrl reg\n");
318 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
319 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
320 printf("Error writing PHY LED reg\n");
323 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
325 #elif defined(CONFIG_KM_PIGGY4_88E6352)
327 #include <mv88e6352.h>
329 #if defined(CONFIG_KM_NUSA)
330 struct mv88e_sw_reg extsw_conf[] = {
332 * port 0, PIGGY4, autoneg
333 * first the fix for the 1000Mbits Autoneg, this is from
334 * a Marvell errata, the regs are undocumented
336 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
337 { PHY(0), PHY_STATUS, AN1000FIX },
338 { PHY(0), PHY_PAGE, 0 },
339 /* now the real port and phy configuration */
340 { PORT(0), PORT_PHY, NO_SPEED_FOR },
341 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
342 { PHY(0), PHY_1000_CTRL, NO_ADV },
343 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
344 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
347 { PORT(1), PORT_CTRL, PORT_DIS },
348 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
349 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
351 { PORT(2), PORT_CTRL, PORT_DIS },
352 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
353 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
355 { PORT(3), PORT_CTRL, PORT_DIS },
356 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
357 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
358 /* port 4, ICNEV, SerDes, SGMII */
359 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
360 { PORT(4), PORT_PHY, SPEED_1000_FOR },
361 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
362 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
363 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
364 /* port 5, CPU_RGMII */
365 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
366 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
367 FULL_DPX_FOR | SPEED_1000_FOR },
368 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
369 /* port 6, unused, this port has no phy */
370 { PORT(6), PORT_CTRL, PORT_DIS },
373 struct mv88e_sw_reg extsw_conf[] = {};
378 #if defined(CONFIG_KM_MVEXTSW_ADDR)
379 char *name = "egiga0";
381 if (miiphy_set_current_dev(name))
384 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
385 ARRAY_SIZE(extsw_conf));
386 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
391 /* Configure and enable MV88E1118 PHY on the piggy*/
395 unsigned char model, rev;
397 char *name = "egiga0";
399 if (miiphy_set_current_dev(name))
403 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
406 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
409 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
410 if ((oui == PHY_MARVELL_OUI) &&
411 (model == PHY_MARVELL_88E1118R_MODEL)) {
412 /* set page register to 3 */
413 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
414 PHY_MARVELL_PAGE_REG,
415 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
416 printf("Error writing PHY page reg\n");
419 * leds setup as printed on PCB:
420 * LED2 (Link): 0x0 (On Link, Off No Link)
421 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
422 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
424 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
425 PHY_MARVELL_88E1118R_LED_CTRL_REG,
426 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
427 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
428 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
429 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
430 printf("Error writing PHY LED reg\n");
432 /* set page register back to 0 */
433 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
434 PHY_MARVELL_PAGE_REG,
435 PHY_MARVELL_DEFAULT_PAGE))
436 printf("Error writing PHY page reg\n");
442 #if defined(CONFIG_HUSH_INIT_VAR)
443 int hush_init_var(void)
445 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
450 #if defined(CONFIG_SYS_I2C_SOFT)
451 void set_sda(int state)
457 void set_scl(int state)
470 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
474 #if defined(CONFIG_POST)
476 #define KM_POST_EN_L 44
477 #define POST_WORD_OFF 8
479 int post_hotkeys_pressed(void)
481 #if defined(CONFIG_KM_COGE5UN)
482 return kw_gpio_get_value(KM_POST_EN_L);
484 return !kw_gpio_get_value(KM_POST_EN_L);
488 ulong post_word_load(void)
490 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
491 return in_le32(addr);
494 void post_word_store(ulong value)
496 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
497 out_le32(addr, value);
500 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
502 *vstart = CONFIG_SYS_SDRAM_BASE;
504 /* we go up to relocation plus a 1 MB margin */
505 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
511 #if defined(CONFIG_SYS_EEPROM_WREN)
512 int eeprom_write_enable(unsigned dev_addr, int state)
514 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
516 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);