3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/soc.h>
24 #include <asm/arch/mpp.h>
26 #include "../common/common.h"
28 DECLARE_GLOBAL_DATA_PTR;
31 * BOCO FPGA definitions
34 #define REG_CTRL_H 0x02
35 #define MASK_WRL_UNITRUN 0x01
36 #define MASK_RBX_PGY_PRESENT 0x40
37 #define REG_IRQ_CIRQ2 0x2d
38 #define MASK_RBI_DEFECT_16 0x01
41 * PHY registers definitions
43 #define PHY_MARVELL_OUI 0x5043
44 #define PHY_MARVELL_88E1118_MODEL 0x0022
45 #define PHY_MARVELL_88E1118R_MODEL 0x0024
47 #define PHY_MARVELL_PAGE_REG 0x0016
48 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
50 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
51 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
53 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
58 /* I/O pin to erase flash RGPP09 = MPP43 */
59 #define KM_FLASH_ERASE_ENABLE 43
61 /* Multi-Purpose Pins Functionality configuration */
62 static const u32 kwmpp_config[] = {
70 #if defined(KM_PCIE_RESET_MPP7)
75 #if defined(CONFIG_SYS_I2C_SOFT)
81 MPP12_GPO, /* Reserved */
84 MPP15_GPIO, /* Not used */
85 MPP16_GPIO, /* Not used */
86 MPP17_GPIO, /* Reserved */
103 MPP34_GPIO, /* CDL1 (input) */
104 MPP35_GPIO, /* CDL2 (input) */
105 MPP36_GPIO, /* MAIN_IRQ (input) */
106 MPP37_GPIO, /* BOARD_LED */
107 MPP38_GPIO, /* Piggy3 LED[1] */
108 MPP39_GPIO, /* Piggy3 LED[2] */
109 MPP40_GPIO, /* Piggy3 LED[3] */
110 MPP41_GPIO, /* Piggy3 LED[4] */
111 MPP42_GPIO, /* Piggy3 LED[5] */
112 MPP43_GPIO, /* Piggy3 LED[6] */
113 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
114 MPP45_GPIO, /* Piggy3 LED[8] */
115 MPP46_GPIO, /* Reserved */
116 MPP47_GPIO, /* Reserved */
117 MPP48_GPIO, /* Reserved */
118 MPP49_GPIO, /* SW_INTOUTn */
122 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
124 #if defined(CONFIG_KM_MGCOGE3UN)
126 * Wait for startup OK from mgcoge3ne
128 static int startup_allowed(void)
133 * Read CIRQ16 bit (bit 0)
135 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
136 printf("%s: Error reading Boco\n", __func__);
138 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
144 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
146 * All boards with PIGGY4 connected via a simple switch have ethernet always
149 int ethernet_present(void)
154 int ethernet_present(void)
159 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
160 printf("%s: Error reading Boco\n", __func__);
163 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
170 static int initialize_unit_leds(void)
173 * Init the unit LEDs per default they all are
174 * ok apart from bootstat
178 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
179 printf("%s: Error reading Boco\n", __func__);
182 buf |= MASK_WRL_UNITRUN;
183 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
184 printf("%s: Error writing Boco\n", __func__);
190 static void set_bootcount_addr(void)
193 unsigned int bootcountaddr;
194 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
195 sprintf((char *)buf, "0x%x", bootcountaddr);
196 setenv("bootcountaddr", (char *)buf);
199 int misc_init_r(void)
201 #if defined(CONFIG_KM_MGCOGE3UN)
203 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
204 wait_for_ne = getenv("waitforne");
206 if ((wait_for_ne != NULL) && (dip_switch == 0)) {
207 if (strcmp(wait_for_ne, "true") == 0) {
211 while (startup_allowed() == 0) {
213 (void) getc(); /* consume input */
220 puts("wait\b\b\b\b");
227 printf("\nAbort waiting for ne\n");
234 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
236 initialize_unit_leds();
238 set_bootcount_addr();
242 int board_early_init_f(void)
244 #if defined(CONFIG_SYS_I2C_SOFT)
247 /* set the 2 bitbang i2c pins as output gpios */
248 tmp = readl(MVEBU_GPIO0_BASE + 4);
249 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
251 /* adjust SDRAM size for bank 0 */
252 mvebu_sdram_size_adjust(0);
253 kirkwood_mpp_conf(kwmpp_config, NULL);
259 /* address of boot parameters */
260 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
263 * The KM_FLASH_GPIO_PIN switches between using a
264 * NAND or a SPI FLASH. Set this pin on start
267 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
268 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
270 #if defined(CONFIG_SYS_I2C_SOFT)
272 * Reinit the GPIO for I2C Bitbang driver so that the now
273 * available gpio framework is consistent. The calls to
274 * direction output in are not necessary, they are already done in
277 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
278 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
281 #if defined(CONFIG_SYS_EEPROM_WREN)
282 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
283 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
286 #if defined(CONFIG_KM_FPGA_CONFIG)
287 trigger_fpga_config();
293 int board_late_init(void)
295 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
296 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
298 /* if pin 1 do full erase */
299 if (dip_switch != 0) {
300 /* start bootloader */
301 puts("DIP: Enabled\n");
302 setenv("actual_bank", "0");
306 #if defined(CONFIG_KM_FPGA_CONFIG)
307 wait_for_fpga_config();
309 toggle_eeprom_spi_bus();
314 int board_spi_claim_bus(struct spi_slave *slave)
316 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
321 void board_spi_release_bus(struct spi_slave *slave)
323 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
326 #if (defined(CONFIG_KM_PIGGY4_88E6061))
328 #define PHY_LED_SEL_REG 0x18
329 #define PHY_LED0_LINK (0x5)
330 #define PHY_LED1_ACT (0x8<<4)
331 #define PHY_LED2_INT (0xe<<8)
332 #define PHY_SPEC_CTRL_REG 0x1c
333 #define PHY_RGMII_CLK_STABLE (0x1<<10)
334 #define PHY_CLSA (0x1<<1)
336 /* Configure and enable MV88E3018 PHY */
339 char *name = "egiga0";
342 if (miiphy_set_current_dev(name))
345 /* RGMII clk transition on data stable */
346 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
347 printf("Error reading PHY spec ctrl reg\n");
348 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
349 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
350 printf("Error writing PHY spec ctrl reg\n");
353 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
354 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
355 printf("Error writing PHY LED reg\n");
358 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
360 #elif defined(CONFIG_KM_PIGGY4_88E6352)
362 #include <mv88e6352.h>
364 #if defined(CONFIG_KM_NUSA)
365 struct mv88e_sw_reg extsw_conf[] = {
367 * port 0, PIGGY4, autoneg
368 * first the fix for the 1000Mbits Autoneg, this is from
369 * a Marvell errata, the regs are undocumented
371 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
372 { PHY(0), PHY_STATUS, AN1000FIX },
373 { PHY(0), PHY_PAGE, 0 },
374 /* now the real port and phy configuration */
375 { PORT(0), PORT_PHY, NO_SPEED_FOR },
376 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
377 { PHY(0), PHY_1000_CTRL, NO_ADV },
378 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
379 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
382 { PORT(1), PORT_CTRL, PORT_DIS },
383 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
384 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
386 { PORT(2), PORT_CTRL, PORT_DIS },
387 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
388 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
390 { PORT(3), PORT_CTRL, PORT_DIS },
391 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
392 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
393 /* port 4, ICNEV, SerDes, SGMII */
394 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
395 { PORT(4), PORT_PHY, SPEED_1000_FOR },
396 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
397 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
398 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
399 /* port 5, CPU_RGMII */
400 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
401 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
402 FULL_DPX_FOR | SPEED_1000_FOR },
403 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
404 /* port 6, unused, this port has no phy */
405 { PORT(6), PORT_CTRL, PORT_DIS },
408 struct mv88e_sw_reg extsw_conf[] = {};
413 #if defined(CONFIG_KM_MVEXTSW_ADDR)
414 char *name = "egiga0";
416 if (miiphy_set_current_dev(name))
419 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
420 ARRAY_SIZE(extsw_conf));
421 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
426 /* Configure and enable MV88E1118 PHY on the piggy*/
430 unsigned char model, rev;
432 char *name = "egiga0";
434 if (miiphy_set_current_dev(name))
438 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
441 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
444 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
445 if ((oui == PHY_MARVELL_OUI) &&
446 (model == PHY_MARVELL_88E1118R_MODEL)) {
447 /* set page register to 3 */
448 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
449 PHY_MARVELL_PAGE_REG,
450 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
451 printf("Error writing PHY page reg\n");
454 * leds setup as printed on PCB:
455 * LED2 (Link): 0x0 (On Link, Off No Link)
456 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
457 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
459 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
460 PHY_MARVELL_88E1118R_LED_CTRL_REG,
461 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
462 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
463 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
464 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
465 printf("Error writing PHY LED reg\n");
467 /* set page register back to 0 */
468 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
469 PHY_MARVELL_PAGE_REG,
470 PHY_MARVELL_DEFAULT_PAGE))
471 printf("Error writing PHY page reg\n");
477 #if defined(CONFIG_HUSH_INIT_VAR)
478 int hush_init_var(void)
480 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
485 #if defined(CONFIG_SYS_I2C_SOFT)
486 void set_sda(int state)
492 void set_scl(int state)
505 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
509 #if defined(CONFIG_POST)
511 #define KM_POST_EN_L 44
512 #define POST_WORD_OFF 8
514 int post_hotkeys_pressed(void)
516 #if defined(CONFIG_KM_COGE5UN)
517 return kw_gpio_get_value(KM_POST_EN_L);
519 return !kw_gpio_get_value(KM_POST_EN_L);
523 ulong post_word_load(void)
525 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
526 return in_le32(addr);
529 void post_word_store(ulong value)
531 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
532 out_le32(addr, value);
535 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
537 *vstart = CONFIG_SYS_SDRAM_BASE;
539 /* we go up to relocation plus a 1 MB margin */
540 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
546 #if defined(CONFIG_SYS_EEPROM_WREN)
547 int eeprom_write_enable(unsigned dev_addr, int state)
549 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
551 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);