2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on U-Boot and RedBoot sources for several different i.mx
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/macro.h>
12 #include <asm/arch/macro.h>
18 * first enable CLKO debug output
19 * 0x40000000 enables the debug CLKO signal
20 * 0x05000000 sets CLKO divider to 6
21 * 0x00600000 makes CLKO parent clk the USB clk
23 write32 0x53f80064, 0x45600000
25 /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
26 write32 0x53f80008, 0x20034000
29 * PCDR2: NFC = 33.25 MHz
30 * This is required for the NAND Flash of this board, which is a Samsung
31 * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
32 * the NFC driver in symmetric (i.e. one-cycle) mode.
34 write32 0x53f80020, 0x01010103
37 * enable all implemented clocks in all three
38 * clock control registers
40 write32 0x53f8000c, 0x1fffffff
41 write32 0x53f80010, 0xffffffff
42 write32 0x53f80014, 0xfdfff
47 * ddr_type is 3.3v SDRAM
49 write32 0x43fac454, 0x800
53 * sdram controller init
55 .macro init_sdram_bank bankaddr, ctl, cfg
59 * reset SDRAM controller
60 * then wait for initialization to complete
64 1: ldr r3, [r0, #0x10]
69 str r1, [r0, #\cfg] /* config */
71 ldr r1, =0x92116480 /* control | precharge */
72 str r1, [r0, #\ctl] /* write command to controller */
73 str r1, [r2, #0x400] /* command encoded in address */
75 ldr r1, =0xa2116480 /* auto refresh */
77 ldrb r3, [r2] /* read dram twice to auto refresh */
80 ldr r1, =0xb2116480 /* control | load mode */
81 str r1, [r0, #\ctl] /* write command to controller */
82 strb r1, [r2, #0x33] /* command encoded in address */
84 ldr r1, =0x82116480 /* control | normal (0)*/
85 str r1, [r0, #\ctl] /* write command to controller */
95 init_sdram_bank 0x80000000, 0x0, 0x4
97 init_sdram_bank 0x90000000, 0x8, 0xc