3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/ixp425.h>
39 #include <asm/arch/ixp425pci.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 #define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */
46 int board_early_init_f(void)
49 writel(0xbcff0002, IXP425_EXP_CS2);
50 writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */
56 #ifndef CONFIG_PCI_PNP
57 static struct pci_config_table pci_ixpdp425_config_table[] = {
58 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID,
59 pci_cfgfunc_config_device,
62 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
64 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID,
65 pci_cfgfunc_config_device,
68 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
70 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID,
71 pci_cfgfunc_config_device,
74 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
76 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID,
77 pci_cfgfunc_config_device,
80 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
85 struct pci_controller hose = {
86 #ifndef CONFIG_PCI_PNP
87 config_table: pci_ixpdp425_config_table,
90 #endif /* CONFIG_PCI */
94 * Miscelaneous platform dependent initialisations
98 writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */
100 #ifdef CONFIG_IXDPG425
101 /* arch number of IXDP */
102 gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
104 /* arch number of IXDP */
105 gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
108 /* adress of boot parameters */
109 gd->bd->bi_boot_params = 0x00000100;
111 #ifdef CONFIG_IXDPG425
113 * Get realtek RTL8305 switch and SLIC out of reset
115 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SWITCH_RESET_N);
116 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SWITCH_RESET_N);
117 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
118 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);
121 * Setup GPIOs for PCI INTA & INTB
123 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N);
124 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N);
125 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N);
126 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);
128 /* Setup GPIOs for 33MHz clock output */
129 writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
131 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
132 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
134 /* set GPIO8..11 interrupt type to active low */
135 writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
137 /* clear pending interrupts */
138 writel(-1, IXP425_GPIO_GPISR);
140 /* assert PCI reset */
141 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N);
145 /* deassert PCI reset */
146 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
151 /* Setup GPIOs for 33MHz ExpBus and PCI clock output */
152 writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
153 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
154 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
155 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N);
157 /* set GPIO8..11 interrupt type to active low */
158 writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
159 /* clear pending interrupts */
160 writel(-1, IXP425_GPIO_GPISR);
162 /* assert PCI reset */
163 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N);
167 /* deassert PCI reset */
168 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N);
177 * Check Board Identity
182 int i = getenv_f("serial#", buf, sizeof(buf));
184 #ifdef CONFIG_IXDPG425
185 puts("Board: IXDPG425 - Intel Network Gateway Reference Platform");
187 puts("Board: IXDP425 - Intel Development Platform");
201 /* we can only map 64MB via PCI, so we limit memory
202 until a better solution is implemented. */
204 gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20);
206 gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20);
212 void pci_init_board(void)
218 * dev 0 on the PCI bus is not the host bridge, so we have to override
219 * these functions in order to not skip PCI slot 0 during configuration.
221 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
225 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
232 int board_eth_init(bd_t *bis)
237 return cpu_eth_init(bis);