3 * ISEE 2007 SL, <www.iseebcn.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mem.h>
13 #include <asm/arch/mmc_host_def.h>
14 #include <asm/arch/mux.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-types.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #if defined(CONFIG_CMD_NET)
22 /* GPMC definitions for LAN9221 chips */
23 static const u32 gpmc_lan_config[] = {
24 NET_LAN9221_GPMC_CONFIG1,
25 NET_LAN9221_GPMC_CONFIG2,
26 NET_LAN9221_GPMC_CONFIG3,
27 NET_LAN9221_GPMC_CONFIG4,
28 NET_LAN9221_GPMC_CONFIG5,
29 NET_LAN9221_GPMC_CONFIG6,
35 * Description: Early hardware init.
39 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
41 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
46 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
47 void show_boot_progress(int val)
50 /* something went wrong */
54 if (!gpio_request(IGEP00X0_GPIO_LED, ""))
55 gpio_direction_output(IGEP00X0_GPIO_LED, 1);
59 #ifdef CONFIG_SPL_BUILD
61 * Routine: omap_rev_string
62 * Description: For SPL builds output board rev
64 void omap_rev_string(void)
69 * Routine: get_board_mem_timings
70 * Description: If we use SPL then there is no x-loader nor config header
71 * so we have to setup the DDR timings ourself on both banks.
73 void get_board_mem_timings(struct board_sdrc_timings *timings)
75 timings->mr = MICRON_V_MR_165;
76 #ifdef CONFIG_BOOT_NAND
77 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
78 timings->ctrla = MICRON_V_ACTIMA_200;
79 timings->ctrlb = MICRON_V_ACTIMB_200;
80 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
82 if (get_cpu_family() == CPU_OMAP34XX) {
83 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
84 timings->ctrla = NUMONYX_V_ACTIMA_165;
85 timings->ctrlb = NUMONYX_V_ACTIMB_165;
86 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
89 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
90 timings->ctrla = NUMONYX_V_ACTIMA_200;
91 timings->ctrlb = NUMONYX_V_ACTIMB_200;
92 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
98 #if defined(CONFIG_CMD_NET)
100 * Routine: setup_net_chip
101 * Description: Setting up the configuration GPMC registers specific to the
104 static void setup_net_chip(void)
106 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
108 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
111 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
112 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
113 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
114 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
115 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
116 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
117 &ctrl_base->gpmc_nadv_ale);
119 /* Make GPIO 64 as output pin and send a magic pulse through it */
120 if (!gpio_request(64, "")) {
121 gpio_direction_output(64, 0);
122 gpio_set_value(64, 1);
124 gpio_set_value(64, 0);
126 gpio_set_value(64, 1);
130 static inline void setup_net_chip(void) {}
133 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
134 int board_mmc_init(bd_t *bis)
136 return omap_mmc_init(0, 0, 0, -1, -1);
142 switch (gd->bd->bi_arch_number) {
143 case MACH_TYPE_IGEP0020:
144 setenv("dtbfile", "omap3-igep0020.dtb");
146 case MACH_TYPE_IGEP0030:
147 setenv("dtbfile", "omap3-igep0030.dtb");
153 * Routine: misc_init_r
154 * Description: Configure board specific parts
156 int misc_init_r(void)
158 twl4030_power_init();
170 * Routine: set_muxconf_regs
171 * Description: Setting up the configuration Mux registers specific to the
172 * hardware. Many pins need to be moved from protect to primary
175 void set_muxconf_regs(void)
179 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
183 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
188 #if defined(CONFIG_CMD_NET)
189 int board_eth_init(bd_t *bis)
192 #ifdef CONFIG_SMC911X
193 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);