board/isee/igep003x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
   4  *
   5  * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <errno.h>
  11 #include <init.h>
  12 #include <malloc.h>
  13 #include <net.h>
  14 #include <serial.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include <fdt_support.h>
  31 #include <mtd_node.h>
  32 #include <jffs2/load_kernel.h>
  33 #include "board.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  38  * and control IGEP0034 green and red LEDs.
  39  * U-boot configures these pins as input pullup to detect board revision:
  40  * IGEP0034-LITE = 0b00
  41  * IGEP0034 (FULL) = 0b01
  42  * IGEP0033 = 0b1X
  43  */
  44 #define GPIO_GREEN_REVISION     27
  45 #define GPIO_RED_REVISION       26
  46
  47 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  48
  49 /*
  50  * Routine: get_board_revision
  51  * Description: Returns the board revision
  52  */
  53 static int get_board_revision(void)
  54 {
  55         int revision;
  56
  57         gpio_request(GPIO_GREEN_REVISION, "green_revision");
  58         gpio_direction_input(GPIO_GREEN_REVISION);
  59         revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  60         gpio_free(GPIO_GREEN_REVISION);
  61
  62         gpio_request(GPIO_RED_REVISION, "red_revision");
  63         gpio_direction_input(GPIO_RED_REVISION);
  64         revision = revision + gpio_get_value(GPIO_RED_REVISION);
  65         gpio_free(GPIO_RED_REVISION);
  66
  67         return revision;
  68 }
  69
  70 #ifdef CONFIG_SPL_BUILD
  71 /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  72 static const struct ddr_data ddr3_igep0034_data = {
  73         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  74         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  75         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  76         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  77 };
  78
  79 static const struct ddr_data ddr3_igep0034_lite_data = {
  80         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  81         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  82         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  83         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  84 };
  85
  86 static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  87         .cmd0csratio = MT41K256M16HA125E_RATIO,
  88         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  89
  90         .cmd1csratio = MT41K256M16HA125E_RATIO,
  91         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  92
  93         .cmd2csratio = MT41K256M16HA125E_RATIO,
  94         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  95 };
  96
  97 static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  98         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  99         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 100
 101         .cmd1csratio = K4B2G1646EBIH9_RATIO,
 102         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 103
 104         .cmd2csratio = K4B2G1646EBIH9_RATIO,
 105         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 106 };
 107
 108 static struct emif_regs ddr3_igep0034_emif_reg_data = {
 109         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 110         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 111         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 112         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 113         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 114         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 115         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 116 };
 117
 118 static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
 119         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
 120         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
 121         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
 122         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
 123         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
 124         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
 125         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 126 };
 127
 128 const struct ctrl_ioregs ioregs_igep0034 = {
 129         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 130         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 131         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 132         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 133         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 134 };
 135
 136 const struct ctrl_ioregs ioregs_igep0034_lite = {
 137         .cm0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 138         .cm1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 139         .cm2ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 140         .dt0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 141         .dt1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
 142 };
 143
 144 #define OSC    (V_OSCK/1000000)
 145 const struct dpll_params dpll_ddr = {
 146                 400, OSC-1, 1, -1, -1, -1, -1};
 147
 148 const struct dpll_params *get_dpll_ddr_params(void)
 149 {
 150         return &dpll_ddr;
 151 }
 152
 153 void set_uart_mux_conf(void)
 154 {
 155         enable_uart0_pin_mux();
 156 }
 157
 158 void set_mux_conf_regs(void)
 159 {
 160         enable_board_pin_mux();
 161 }
 162
 163 void sdram_init(void)
 164 {
 165         if (get_board_revision() == 1)
 166                 config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
 167                         &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
 168         else
 169                 config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
 170                         &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
 171 }
 172
 173 #ifdef CONFIG_SPL_OS_BOOT
 174 int spl_start_uboot(void)
 175 {
 176         /* break into full u-boot on 'c' */
 177         return serial_tstc() && serial_getc() == 'c';
 178 }
 179 #endif
 180 #endif
 181
 182 /*
 183  * Basic board specific setup.  Pinmux has been handled already.
 184  */
 185 int board_init(void)
 186 {
 187         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 188
 189         gpmc_init();
 190
 191         return 0;
 192 }
 193
 194 #ifdef CONFIG_BOARD_LATE_INIT
 195 int board_late_init(void)
 196 {
 197 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 198         switch (get_board_revision()) {
 199                 case 0:
 200                         env_set("board_name", "igep0034-lite");
 201                         break;
 202                 case 1:
 203                         env_set("board_name", "igep0034");
 204                         break;
 205                 default:
 206                         env_set("board_name", "igep0033");
 207                         break;
 208         }
 209 #endif
 210         return 0;
 211 }
 212 #endif
 213
 214 #ifdef CONFIG_OF_BOARD_SETUP
 215 int ft_board_setup(void *blob, bd_t *bd)
 216 {
 217 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 218         static const struct node_info nodes[] = {
 219                 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
 220         };
 221
 222         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 223 #endif
 224         return 0;
 225 }
 226 #endif
 227
 228 #if defined(CONFIG_DRIVER_TI_CPSW)
 229 static void cpsw_control(int enabled)
 230 {
 231         /* VTP can be added here */
 232
 233         return;
 234 }
 235
 236 static struct cpsw_slave_data cpsw_slaves[] = {
 237         {
 238                 .slave_reg_ofs  = 0x208,
 239                 .sliver_reg_ofs = 0xd80,
 240                 .phy_addr       = 0,
 241                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 242         },
 243 };
 244
 245 static struct cpsw_platform_data cpsw_data = {
 246         .mdio_base              = CPSW_MDIO_BASE,
 247         .cpsw_base              = CPSW_BASE,
 248         .mdio_div               = 0xff,
 249         .channels               = 8,
 250         .cpdma_reg_ofs          = 0x800,
 251         .slaves                 = 1,
 252         .slave_data             = cpsw_slaves,
 253         .ale_reg_ofs            = 0xd00,
 254         .ale_entries            = 1024,
 255         .host_port_reg_ofs      = 0x108,
 256         .hw_stats_reg_ofs       = 0x900,
 257         .bd_ram_ofs             = 0x2000,
 258         .mac_control            = (1 << 5),
 259         .control                = cpsw_control,
 260         .host_port_num          = 0,
 261         .version                = CPSW_CTRL_VERSION_2,
 262 };
 263
 264 int board_eth_init(bd_t *bis)
 265 {
 266         int rv, ret = 0;
 267         uint8_t mac_addr[6];
 268         uint32_t mac_hi, mac_lo;
 269
 270         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 271                 /* try reading mac address from efuse */
 272                 mac_lo = readl(&cdev->macid0l);
 273                 mac_hi = readl(&cdev->macid0h);
 274                 mac_addr[0] = mac_hi & 0xFF;
 275                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 276                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 277                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 278                 mac_addr[4] = mac_lo & 0xFF;
 279                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 280                 if (is_valid_ethaddr(mac_addr))
 281                         eth_env_set_enetaddr("ethaddr", mac_addr);
 282         }
 283
 284         writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 285                &cdev->miisel);
 286
 287         if (get_board_revision() == 1)
 288                 cpsw_slaves[0].phy_addr = 1;
 289
 290         rv = cpsw_register(&cpsw_data);
 291         if (rv < 0)
 292                 printf("Error %d registering CPSW switch\n", rv);
 293         else
 294                 ret += rv;
 295
 296         return ret;
 297 }
 298 #endif