2 * Board functions for IGEP COM AQUILA based boards
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/omap.h>
15 #include <asm/arch/ddr_defs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/mmc_host_def.h>
19 #include <asm/arch/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* MII mode defines */
31 #define RMII_MODE_ENABLE 0x4D
33 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
35 #ifdef CONFIG_SPL_BUILD
36 static const struct ddr_data ddr3_data = {
37 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
38 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
39 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
40 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
41 .datadldiff0 = PHY_DLL_LOCK_DIFF,
44 static const struct cmd_control ddr3_cmd_ctrl_data = {
45 .cmd0csratio = K4B2G1646EBIH9_RATIO,
46 .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
47 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
49 .cmd1csratio = K4B2G1646EBIH9_RATIO,
50 .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
51 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
53 .cmd2csratio = K4B2G1646EBIH9_RATIO,
54 .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
55 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
58 static struct emif_regs ddr3_emif_reg_data = {
59 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
60 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
61 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
62 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
63 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
64 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
65 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
68 #define OSC (V_OSCK/1000000)
69 const struct dpll_params dpll_ddr = {
70 303, OSC-1, 1, -1, -1, -1, -1};
72 const struct dpll_params *get_dpll_ddr_params(void)
77 void set_uart_mux_conf(void)
79 enable_uart0_pin_mux();
82 void set_mux_conf_regs(void)
84 enable_board_pin_mux();
89 config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
90 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
95 * Basic board specific setup. Pinmux has been handled already.
99 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
106 #if defined(CONFIG_DRIVER_TI_CPSW)
107 static void cpsw_control(int enabled)
109 /* VTP can be added here */
114 static struct cpsw_slave_data cpsw_slaves[] = {
116 .slave_reg_ofs = 0x208,
117 .sliver_reg_ofs = 0xd80,
119 .phy_if = PHY_INTERFACE_MODE_RMII,
123 static struct cpsw_platform_data cpsw_data = {
124 .mdio_base = CPSW_MDIO_BASE,
125 .cpsw_base = CPSW_BASE,
128 .cpdma_reg_ofs = 0x800,
130 .slave_data = cpsw_slaves,
131 .ale_reg_ofs = 0xd00,
133 .host_port_reg_ofs = 0x108,
134 .hw_stats_reg_ofs = 0x900,
135 .mac_control = (1 << 5),
136 .control = cpsw_control,
138 .version = CPSW_CTRL_VERSION_2,
141 int board_eth_init(bd_t *bis)
145 uint32_t mac_hi, mac_lo;
147 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
148 /* try reading mac address from efuse */
149 mac_lo = readl(&cdev->macid0l);
150 mac_hi = readl(&cdev->macid0h);
151 mac_addr[0] = mac_hi & 0xFF;
152 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
153 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
154 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
155 mac_addr[4] = mac_lo & 0xFF;
156 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
157 if (is_valid_ether_addr(mac_addr))
158 eth_setenv_enetaddr("ethaddr", mac_addr);
161 writel(RMII_MODE_ENABLE, &cdev->miisel);
163 rv = cpsw_register(&cpsw_data);
165 printf("Error %d registering CPSW switch\n", rv);