2 * Board functions for IGEP COM AQUILA based boards
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/omap.h>
15 #include <asm/arch/ddr_defs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/mmc_host_def.h>
19 #include <asm/arch/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
32 #ifdef CONFIG_SPL_BUILD
33 static const struct ddr_data ddr3_data = {
34 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
35 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
36 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
37 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
40 static const struct cmd_control ddr3_cmd_ctrl_data = {
41 .cmd0csratio = K4B2G1646EBIH9_RATIO,
42 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
44 .cmd1csratio = K4B2G1646EBIH9_RATIO,
45 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
47 .cmd2csratio = K4B2G1646EBIH9_RATIO,
48 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
51 static struct emif_regs ddr3_emif_reg_data = {
52 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
53 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
54 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
55 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
56 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
57 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
58 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
61 #define OSC (V_OSCK/1000000)
62 const struct dpll_params dpll_ddr = {
63 400, OSC-1, 1, -1, -1, -1, -1};
65 const struct dpll_params *get_dpll_ddr_params(void)
70 void set_uart_mux_conf(void)
72 enable_uart0_pin_mux();
75 void set_mux_conf_regs(void)
77 enable_board_pin_mux();
80 const struct ctrl_ioregs ioregs = {
81 .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
82 .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
83 .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
84 .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
85 .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
90 config_ddr(400, &ioregs, &ddr3_data,
91 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
96 * Basic board specific setup. Pinmux has been handled already.
100 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
107 #if defined(CONFIG_DRIVER_TI_CPSW)
108 static void cpsw_control(int enabled)
110 /* VTP can be added here */
115 static struct cpsw_slave_data cpsw_slaves[] = {
117 .slave_reg_ofs = 0x208,
118 .sliver_reg_ofs = 0xd80,
120 .phy_if = PHY_INTERFACE_MODE_RMII,
124 static struct cpsw_platform_data cpsw_data = {
125 .mdio_base = CPSW_MDIO_BASE,
126 .cpsw_base = CPSW_BASE,
129 .cpdma_reg_ofs = 0x800,
131 .slave_data = cpsw_slaves,
132 .ale_reg_ofs = 0xd00,
134 .host_port_reg_ofs = 0x108,
135 .hw_stats_reg_ofs = 0x900,
136 .bd_ram_ofs = 0x2000,
137 .mac_control = (1 << 5),
138 .control = cpsw_control,
140 .version = CPSW_CTRL_VERSION_2,
143 int board_eth_init(bd_t *bis)
147 uint32_t mac_hi, mac_lo;
149 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
150 /* try reading mac address from efuse */
151 mac_lo = readl(&cdev->macid0l);
152 mac_hi = readl(&cdev->macid0h);
153 mac_addr[0] = mac_hi & 0xFF;
154 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
155 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
156 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
157 mac_addr[4] = mac_lo & 0xFF;
158 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
159 if (is_valid_ether_addr(mac_addr))
160 eth_setenv_enetaddr("ethaddr", mac_addr);
163 writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
166 rv = cpsw_register(&cpsw_data);
168 printf("Error %d registering CPSW switch\n", rv);