board/isee/igep0033/board.c

   1 /*
   2  * Board functions for IGEP COM AQUILA/CYGNUS based boards
   3  *
   4  * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <spl.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/io.h>
  29 #include <asm/emif.h>
  30 #include <asm/gpio.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include "board.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  39 #ifdef CONFIG_SPL_BUILD
  40 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  41 #endif
  42
  43 /* MII mode defines */
  44 #define RMII_MODE_ENABLE        0x4D
  45
  46 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  47
  48 /* UART Defines */
  49 #ifdef CONFIG_SPL_BUILD
  50 #define UART_RESET              (0x1 << 1)
  51 #define UART_CLK_RUNNING_MASK   0x1
  52 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
  53
  54 static const struct ddr_data ddr3_data = {
  55         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  56         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  57         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  58         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  59         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  60 };
  61
  62 static const struct cmd_control ddr3_cmd_ctrl_data = {
  63         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  64         .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  65         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  66
  67         .cmd1csratio = K4B2G1646EBIH9_RATIO,
  68         .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  69         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  70
  71         .cmd2csratio = K4B2G1646EBIH9_RATIO,
  72         .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  73         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  74 };
  75
  76 static struct emif_regs ddr3_emif_reg_data = {
  77         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  78         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  79         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  80         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  81         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  82         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  83         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  84 };
  85 #endif
  86
  87 /*
  88  * Early system init of muxing and clocks.
  89  */
  90 void s_init(void)
  91 {
  92         /*
  93          * Save the boot parameters passed from romcode.
  94          * We cannot delay the saving further than this,
  95          * to prevent overwrites.
  96          */
  97 #ifdef CONFIG_SPL_BUILD
  98         save_omap_boot_params();
  99 #endif
 100
 101         /* WDT1 is already running when the bootloader gets control
 102          * Disable it to avoid "random" resets
 103          */
 104         writel(0xAAAA, &wdtimer->wdtwspr);
 105         while (readl(&wdtimer->wdtwwps) != 0x0)
 106                 ;
 107         writel(0x5555, &wdtimer->wdtwspr);
 108         while (readl(&wdtimer->wdtwwps) != 0x0)
 109                 ;
 110
 111 #ifdef CONFIG_SPL_BUILD
 112         /* Setup the PLLs and the clocks for the peripherals */
 113         pll_init();
 114
 115         /* Enable RTC32K clock */
 116         rtc32k_enable();
 117
 118         /* UART softreset */
 119         u32 regval;
 120
 121         enable_uart0_pin_mux();
 122
 123         regval = readl(&uart_base->uartsyscfg);
 124         regval |= UART_RESET;
 125         writel(regval, &uart_base->uartsyscfg);
 126         while ((readl(&uart_base->uartsyssts) &
 127                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 128                 ;
 129
 130         /* Disable smart idle */
 131         regval = readl(&uart_base->uartsyscfg);
 132         regval |= UART_SMART_IDLE_EN;
 133         writel(regval, &uart_base->uartsyscfg);
 134
 135         gd = &gdata;
 136
 137         preloader_console_init();
 138
 139         /* Configure board pin mux */
 140         enable_board_pin_mux();
 141
 142         config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
 143                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 144 #endif
 145 }
 146
 147 /*
 148  * Basic board specific setup.  Pinmux has been handled already.
 149  */
 150 int board_init(void)
 151 {
 152         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 153
 154         gpmc_init();
 155
 156         return 0;
 157 }
 158
 159 #if defined(CONFIG_DRIVER_TI_CPSW)
 160 static void cpsw_control(int enabled)
 161 {
 162         /* VTP can be added here */
 163
 164         return;
 165 }
 166
 167 static struct cpsw_slave_data cpsw_slaves[] = {
 168         {
 169                 .slave_reg_ofs  = 0x208,
 170                 .sliver_reg_ofs = 0xd80,
 171                 .phy_id         = 0,
 172                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 173         },
 174 };
 175
 176 static struct cpsw_platform_data cpsw_data = {
 177         .mdio_base              = CPSW_MDIO_BASE,
 178         .cpsw_base              = CPSW_BASE,
 179         .mdio_div               = 0xff,
 180         .channels               = 8,
 181         .cpdma_reg_ofs          = 0x800,
 182         .slaves                 = 1,
 183         .slave_data             = cpsw_slaves,
 184         .ale_reg_ofs            = 0xd00,
 185         .ale_entries            = 1024,
 186         .host_port_reg_ofs      = 0x108,
 187         .hw_stats_reg_ofs       = 0x900,
 188         .mac_control            = (1 << 5),
 189         .control                = cpsw_control,
 190         .host_port_num          = 0,
 191         .version                = CPSW_CTRL_VERSION_2,
 192 };
 193
 194 int board_eth_init(bd_t *bis)
 195 {
 196         int rv, ret = 0;
 197         uint8_t mac_addr[6];
 198         uint32_t mac_hi, mac_lo;
 199
 200         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 201                 /* try reading mac address from efuse */
 202                 mac_lo = readl(&cdev->macid0l);
 203                 mac_hi = readl(&cdev->macid0h);
 204                 mac_addr[0] = mac_hi & 0xFF;
 205                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 206                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 207                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 208                 mac_addr[4] = mac_lo & 0xFF;
 209                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 210                 if (is_valid_ether_addr(mac_addr))
 211                         eth_setenv_enetaddr("ethaddr", mac_addr);
 212         }
 213
 214         writel(RMII_MODE_ENABLE, &cdev->miisel);
 215
 216         rv = cpsw_register(&cpsw_data);
 217         if (rv < 0)
 218                 printf("Error %d registering CPSW switch\n", rv);
 219         else
 220                 ret += rv;
 221
 222         return ret;
 223 }
 224 #endif
 225