3 * ISEE 2007 SL, <www.iseebcn.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/mem.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/mux.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/mach-types.h>
33 DECLARE_GLOBAL_DATA_PTR;
37 * Description: Early hardware init.
41 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
43 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
48 #ifdef CONFIG_SPL_BUILD
50 * Routine: omap_rev_string
51 * Description: For SPL builds output board rev
53 void omap_rev_string(void)
58 * Routine: get_board_mem_timings
59 * Description: If we use SPL then there is no x-loader nor config header
60 * so we have to setup the DDR timings ourself on both banks.
62 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
65 *mr = MICRON_V_MR_165;
66 #ifdef CONFIG_BOOT_NAND
67 *mcfg = MICRON_V_MCFG_200(256 << 20);
68 *ctrla = MICRON_V_ACTIMA_200;
69 *ctrlb = MICRON_V_ACTIMB_200;
70 *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
72 if (get_cpu_family() == CPU_OMAP34XX) {
73 *mcfg = NUMONYX_V_MCFG_165(256 << 20);
74 *ctrla = NUMONYX_V_ACTIMA_165;
75 *ctrlb = NUMONYX_V_ACTIMB_165;
76 *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
79 *mcfg = NUMONYX_V_MCFG_200(256 << 20);
80 *ctrla = NUMONYX_V_ACTIMA_200;
81 *ctrlb = NUMONYX_V_ACTIMB_200;
82 *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
88 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
89 int board_mmc_init(bd_t *bis)
91 omap_mmc_init(0, 0, 0);
97 * Routine: misc_init_r
98 * Description: Configure board specific parts
100 int misc_init_r(void)
102 twl4030_power_init();
110 * Routine: set_muxconf_regs
111 * Description: Setting up the configuration Mux registers specific to the
112 * hardware. Many pins need to be moved from protect to primary
115 void set_muxconf_regs(void)