3 * ISEE 2007 SL, <www.iseebcn.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mem.h>
29 #include <asm/arch/mux.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/mach-types.h>
34 /* GPMC definitions for LAN9221 chips */
35 static const u32 gpmc_lan_config[] = {
36 NET_LAN9221_GPMC_CONFIG1,
37 NET_LAN9221_GPMC_CONFIG2,
38 NET_LAN9221_GPMC_CONFIG3,
39 NET_LAN9221_GPMC_CONFIG4,
40 NET_LAN9221_GPMC_CONFIG5,
41 NET_LAN9221_GPMC_CONFIG6,
46 * Description: Early hardware init.
50 DECLARE_GLOBAL_DATA_PTR;
52 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
53 /* board id for Linux */
54 gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
56 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
62 * Routine: setup_net_chip
63 * Description: Setting up the configuration GPMC registers specific to the
66 #if defined(CONFIG_CMD_NET)
67 static void setup_net_chip(void)
69 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
71 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
74 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
75 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
76 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
77 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
78 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
79 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
80 &ctrl_base->gpmc_nadv_ale);
82 /* Make GPIO 64 as output pin and send a magic pulse through it */
83 if (!omap_request_gpio(64)) {
84 omap_set_gpio_direction(64, 0);
85 omap_set_gpio_dataout(64, 1);
87 omap_set_gpio_dataout(64, 0);
89 omap_set_gpio_dataout(64, 1);
95 * Routine: misc_init_r
96 * Description: Configure board specific parts
100 twl4030_power_init();
102 #if defined(CONFIG_CMD_NET)
112 * Routine: set_muxconf_regs
113 * Description: Setting up the configuration Mux registers specific to the
114 * hardware. Many pins need to be moved from protect to primary
117 void set_muxconf_regs(void)
122 int board_eth_init(bd_t *bis)
125 #ifdef CONFIG_SMC911X
126 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);