3 * ISEE 2007 SL, <www.iseebcn.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mem.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/mux.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/mach-types.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 /* GPMC definitions for LAN9221 chips */
38 static const u32 gpmc_lan_config[] = {
39 NET_LAN9221_GPMC_CONFIG1,
40 NET_LAN9221_GPMC_CONFIG2,
41 NET_LAN9221_GPMC_CONFIG3,
42 NET_LAN9221_GPMC_CONFIG4,
43 NET_LAN9221_GPMC_CONFIG5,
44 NET_LAN9221_GPMC_CONFIG6,
49 * Description: Early hardware init.
53 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
54 /* board id for Linux */
55 gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
57 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
63 * Routine: setup_net_chip
64 * Description: Setting up the configuration GPMC registers specific to the
67 #if defined(CONFIG_CMD_NET)
68 static void setup_net_chip(void)
70 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
72 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
75 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
76 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
77 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
78 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
79 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
80 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
81 &ctrl_base->gpmc_nadv_ale);
83 /* Make GPIO 64 as output pin and send a magic pulse through it */
84 if (!omap_request_gpio(64)) {
85 omap_set_gpio_direction(64, 0);
86 omap_set_gpio_dataout(64, 1);
88 omap_set_gpio_dataout(64, 0);
90 omap_set_gpio_dataout(64, 1);
95 #ifdef CONFIG_GENERIC_MMC
96 int board_mmc_init(bd_t *bis)
104 * Routine: misc_init_r
105 * Description: Configure board specific parts
107 int misc_init_r(void)
109 twl4030_power_init();
111 #if defined(CONFIG_CMD_NET)
121 * Routine: set_muxconf_regs
122 * Description: Setting up the configuration Mux registers specific to the
123 * hardware. Many pins need to be moved from protect to primary
126 void set_muxconf_regs(void)
131 int board_eth_init(bd_t *bis)
134 #ifdef CONFIG_SMC911X
135 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);