2 * (C) Copyright 2008-2009
3 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
6 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
9 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
12 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
14 * (C) Copyright 2003-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41 #if defined(CONFIG_DDR_MT46V16M16)
42 #include "mt46v16m16-75.h"
43 #elif defined(CONFIG_SDR_MT48LC16M16A2)
44 #include "mt48lc16m16a2-75.h"
45 #elif defined(CONFIG_DDR_MT46V32M16)
46 #include "mt46v32m16.h"
47 #elif defined(CONFIG_DDR_HYB25D512160BF)
48 #include "hyb25d512160bf.h"
49 #elif defined(CONFIG_DDR_K4H511638C)
50 #include "k4h511638c.h"
52 #error "INKA4x0 SDRAM: invalid chip type specified!"
55 #ifndef CONFIG_SYS_RAMBOOT
56 static void sdram_start (int hi_addr)
58 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
60 /* unlock mode register */
61 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
62 __asm__ volatile ("sync");
64 /* precharge all banks */
65 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
66 __asm__ volatile ("sync");
69 /* set mode register: extended mode */
70 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
71 __asm__ volatile ("sync");
73 /* set mode register: reset DLL */
74 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
75 __asm__ volatile ("sync");
78 /* precharge all banks */
79 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
80 __asm__ volatile ("sync");
83 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
84 __asm__ volatile ("sync");
86 /* set mode register */
87 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
88 __asm__ volatile ("sync");
90 /* normal operation */
91 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
92 __asm__ volatile ("sync");
97 * ATTENTION: Although partially referenced initdram does NOT make real use
98 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
99 * is something else than 0x00000000.
102 phys_size_t initdram (int board_type)
105 #ifndef CONFIG_SYS_RAMBOOT
108 /* setup SDRAM chip selects */
109 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
110 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
111 __asm__ volatile ("sync");
113 /* setup config registers */
114 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
115 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
116 __asm__ volatile ("sync");
120 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
121 __asm__ volatile ("sync");
124 /* find RAM size using SDRAM CS0 only */
126 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
128 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
136 /* memory smaller than 1MB is impossible */
137 if (dramsize < (1 << 20)) {
141 /* set SDRAM CS0 size according to the amount of RAM found */
143 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
144 __builtin_ffs(dramsize >> 20) - 1;
146 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
149 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
150 #else /* CONFIG_SYS_RAMBOOT */
152 /* retrieve size of memory connected to SDRAM CS0 */
153 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
154 if (dramsize >= 0x13) {
155 dramsize = (1 << (dramsize - 0x13)) << 20;
159 #endif /* CONFIG_SYS_RAMBOOT */
164 int checkboard (void)
166 puts ("Board: INKA 4X0\n");
170 void flash_preinit(void)
173 * Now, when we are in RAM, enable flash write
174 * access for detection process.
175 * Note that CS_BOOT cannot be cleared when
176 * executing in flash.
178 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
181 int misc_init_r (void) {
182 extern int inkadiag_init_r (void);
185 * The command table used for the subcommands of inkadiag
186 * needs to be relocated manually.
188 return inkadiag_init_r();
191 int misc_init_f (void)
193 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
194 struct mpc5xxx_wu_gpio *wu_gpio = (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
198 i = getenv_r("brightness", tmp, sizeof(tmp));
200 ? (int) simple_strtoul (tmp, NULL, 10)
201 : CONFIG_SYS_BRIGHTNESS;
205 /* Initialize GPIO output pins.
207 /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
208 *(vu_long *)MPC5XXX_GPT0_ENABLE =
209 *(vu_long *)MPC5XXX_GPT1_ENABLE =
210 *(vu_long *)MPC5XXX_GPT2_ENABLE =
211 *(vu_long *)MPC5XXX_GPT3_ENABLE =
212 *(vu_long *)MPC5XXX_GPT4_ENABLE =
213 *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
215 /* Configure GPT7 as PWM timer, 1kHz, no ints. */
216 *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
217 *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
218 *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
219 *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
221 /* Configure PSC3_6,7 as GPIO output */
222 *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
223 *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
225 /* Configure PSC3_8 as GPIO output, no interrupt */
226 *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
227 *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
228 *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
230 /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
231 *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
232 *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
234 /* Set LR mirror bit because it is low-active */
235 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7;
237 * Reset Coral-P graphics controller
239 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
240 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
241 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9;
244 * Configure three wire serial interface to RTC (PSC1_4,
245 * PSC2_4, PSC3_4, PSC3_5)
247 setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 |
248 MPC5XXX_GPIO_WKUP_PSC2_4);
249 setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 |
250 MPC5XXX_GPIO_WKUP_PSC2_4);
251 clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
252 clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
253 MPC5XXX_GPIO_SINT_PSC3_5);
254 setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
255 MPC5XXX_GPIO_SINT_PSC3_5);
256 setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
257 clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
263 static struct pci_controller hose;
265 extern void pci_mpc5xxx_init(struct pci_controller *);
267 void pci_init_board(void)
269 pci_mpc5xxx_init(&hose);
273 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
275 void init_ide_reset (void)
277 debug ("init_ide_reset\n");
279 /* Configure PSC1_4 as GPIO output for ATA reset */
280 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
281 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
283 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
286 void ide_set_reset (int idereset)
288 debug ("ide_reset(%d)\n", idereset);
291 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
292 /* Make a delay. MPC5200 spec says 25 usec min */
295 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;