1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
11 #include <pci_gt64120.h>
12 #include <pci_msc01.h>
15 #include <asm/addrspace.h>
17 #include <asm/malta.h>
21 DECLARE_GLOBAL_DATA_PTR;
35 static void malta_lcd_puts(const char *str)
38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
40 /* print up to 8 characters of the string */
41 for (i = 0; i < min((int)strlen(str), 8); i++) {
42 __raw_writel(str[i], reg);
43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
46 /* fill the rest of the display with spaces */
48 __raw_writel(' ', reg);
49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
53 static enum core_card malta_core_card(void)
56 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
58 rev = __raw_readl(reg);
59 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
62 case MALTA_REVISION_CORID_CORE_LV:
65 case MALTA_REVISION_CORID_CORE_FPGA6:
73 static enum sys_con malta_sys_con(void)
75 switch (malta_core_card()) {
77 return SYSCON_GT64120;
83 return SYSCON_UNKNOWN;
89 gd->ram_size = CONFIG_SYS_MEM_SIZE;
98 malta_lcd_puts("U-Boot");
99 puts("Board: MIPS Malta");
101 core = malta_core_card();
112 puts(" CoreUnknown");
119 int board_eth_init(bd_t *bis)
121 return pci_eth_init(bis);
124 void _machine_restart(void)
126 void __iomem *reset_base;
128 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
129 __raw_writel(GORESET, reset_base);
133 int board_early_init_f(void)
137 /* choose correct PCI I/O base */
138 switch (malta_sys_con()) {
140 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
144 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
151 set_io_port_base(io_base);
153 /* setup FDC37M817 super I/O controller */
154 malta_superio_init();
159 int misc_init_r(void)
166 void pci_init_board(void)
172 switch (malta_sys_con()) {
174 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
175 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
176 0x10000000, 0x10000000, 128 * 1024 * 1024,
177 0x00000000, 0x00000000, 0x20000);
182 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
183 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
184 MALTA_MSC01_PCIMEM_MAP,
185 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
186 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
187 0x00000000, MALTA_MSC01_PCIIO_SIZE);
191 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
192 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
194 panic("Failed to find PIIX4 PCI bridge\n");
196 /* setup PCI interrupt routing */
197 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
198 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
199 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
200 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
202 /* mux SERIRQ onto SERIRQ pin */
203 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
204 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
205 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
207 /* enable SERIRQ - Linux currently depends upon this */
208 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
209 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
210 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
212 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
213 PCI_DEVICE_ID_INTEL_82371AB, 0);
215 panic("Failed to find PIIX4 IDE controller\n");
217 /* enable bus master & IO access */
218 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
219 pci_write_config_dword(bdf, PCI_COMMAND, val32);
222 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
225 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
226 PCI_CFG_PIIX4_IDETIM_IDE);
227 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
228 PCI_CFG_PIIX4_IDETIM_IDE);