1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
13 #include <pci_gt64120.h>
14 #include <pci_msc01.h>
16 #include <linux/delay.h>
18 #include <asm/addrspace.h>
20 #include <asm/malta.h>
24 DECLARE_GLOBAL_DATA_PTR;
38 static void malta_lcd_puts(const char *str)
41 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
43 /* print up to 8 characters of the string */
44 for (i = 0; i < min((int)strlen(str), 8); i++) {
45 __raw_writel(str[i], reg);
46 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
49 /* fill the rest of the display with spaces */
51 __raw_writel(' ', reg);
52 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
56 static enum core_card malta_core_card(void)
59 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
61 rev = __raw_readl(reg);
62 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
65 case MALTA_REVISION_CORID_CORE_LV:
68 case MALTA_REVISION_CORID_CORE_FPGA6:
76 static enum sys_con malta_sys_con(void)
78 switch (malta_core_card()) {
80 return SYSCON_GT64120;
86 return SYSCON_UNKNOWN;
92 gd->ram_size = CONFIG_SYS_MEM_SIZE;
101 malta_lcd_puts("U-Boot");
102 puts("Board: MIPS Malta");
104 core = malta_core_card();
115 puts(" CoreUnknown");
122 int board_eth_init(bd_t *bis)
124 return pci_eth_init(bis);
127 void _machine_restart(void)
129 void __iomem *reset_base;
131 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
132 __raw_writel(GORESET, reset_base);
136 int board_early_init_f(void)
140 /* choose correct PCI I/O base */
141 switch (malta_sys_con()) {
143 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
147 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
154 set_io_port_base(io_base);
156 /* setup FDC37M817 super I/O controller */
157 malta_superio_init();
162 int misc_init_r(void)
169 void pci_init_board(void)
175 switch (malta_sys_con()) {
177 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
178 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
179 0x10000000, 0x10000000, 128 * 1024 * 1024,
180 0x00000000, 0x00000000, 0x20000);
185 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
186 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
187 MALTA_MSC01_PCIMEM_MAP,
188 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
189 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
190 0x00000000, MALTA_MSC01_PCIIO_SIZE);
194 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
195 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
197 panic("Failed to find PIIX4 PCI bridge\n");
199 /* setup PCI interrupt routing */
200 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
201 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
202 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
203 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
205 /* mux SERIRQ onto SERIRQ pin */
206 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
207 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
208 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
210 /* enable SERIRQ - Linux currently depends upon this */
211 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
212 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
213 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
215 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
216 PCI_DEVICE_ID_INTEL_82371AB, 0);
218 panic("Failed to find PIIX4 IDE controller\n");
220 /* enable bus master & IO access */
221 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
222 pci_write_config_dword(bdf, PCI_COMMAND, val32);
225 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
228 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
229 PCI_CFG_PIIX4_IDETIM_IDE);
230 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
231 PCI_CFG_PIIX4_IDETIM_IDE);