2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 * Copyright (C) 2013 Imagination Technologies
5 * SPDX-License-Identifier: GPL-2.0
10 #include <pci_gt64120.h>
11 #include <pci_msc01.h>
15 #include <asm/addrspace.h>
17 #include <asm/malta.h>
33 static void malta_lcd_puts(const char *str)
36 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
38 /* print up to 8 characters of the string */
39 for (i = 0; i < min(strlen(str), 8); i++) {
40 __raw_writel(str[i], reg);
41 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
44 /* fill the rest of the display with spaces */
46 __raw_writel(' ', reg);
47 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
51 static enum core_card malta_core_card(void)
55 rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
56 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
59 case MALTA_REVISION_CORID_CORE_LV:
62 case MALTA_REVISION_CORID_CORE_FPGA6:
70 static enum sys_con malta_sys_con(void)
72 switch (malta_core_card()) {
74 return SYSCON_GT64120;
80 return SYSCON_UNKNOWN;
84 phys_size_t initdram(int board_type)
86 return CONFIG_SYS_MEM_SIZE;
93 malta_lcd_puts("U-boot");
94 puts("Board: MIPS Malta");
96 core = malta_core_card();
107 puts(" CoreUnknown");
114 int board_eth_init(bd_t *bis)
116 return pci_eth_init(bis);
119 void _machine_restart(void)
121 void __iomem *reset_base;
123 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
124 __raw_writel(GORESET, reset_base);
127 int board_early_init_f(void)
131 /* choose correct PCI I/O base */
132 switch (malta_sys_con()) {
134 io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
138 io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
145 /* setup FDC37M817 super I/O controller */
146 malta_superio_init(io_base);
151 int misc_init_r(void)
158 struct serial_device *default_serial_console(void)
160 switch (malta_sys_con()) {
162 return &eserial1_device;
166 return &eserial2_device;
170 void pci_init_board(void)
172 switch (malta_sys_con()) {
174 set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
176 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
177 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
178 0x10000000, 0x10000000, 128 * 1024 * 1024,
179 0x00000000, 0x00000000, 0x20000);
184 set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
186 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
187 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
188 MALTA_MSC01_PCIMEM_MAP,
189 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
190 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
191 0x00000000, MALTA_MSC01_PCIIO_SIZE);