2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2010 ifm ecomatic GmbH
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
16 #include <asm/bitops.h>
19 #include <asm/processor.h>
20 #include <asm/mpc512x.h>
21 #include <fdt_support.h>
22 #ifdef CONFIG_MISC_INIT_R
26 DECLARE_GLOBAL_DATA_PTR;
28 static void gpio_configure(void)
33 im = (immap_t *) CONFIG_SYS_IMMR;
35 out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
36 out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
39 * out_be32(&gpioregs->gpdir, 0xC2293020);
40 * workaround for a hardware affect: configure direction in pieces,
41 * setting all outputs at once drops the reset line too low and
42 * makes us lose the MII connection (breaks ethernet for us)
44 out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
45 setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
47 setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
49 setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
51 setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
53 /* to turn from red to yellow when U-Boot runs */
54 setbits_be32(&gpioregs->gpdat, 0x00002020);
55 out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
56 out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
57 out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
58 out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
61 /* the physical location of the pins */
62 #define GPIOKEY_ROW_BITMASK 0x40000000
63 #define GPIOKEY_ROW_UPPER 0
64 #define GPIOKEY_ROW_LOWER 1
66 #define GPIOKEY_COL0_BITMASK 0x20000000
67 #define GPIOKEY_COL1_BITMASK 0x10000000
68 #define GPIOKEY_COL2_BITMASK 0x08000000
70 /* the logical presentation of pressed keys */
71 #define GPIOKEY_BIT_FNLEFT (1 << 5)
72 #define GPIOKEY_BIT_FNRIGHT (1 << 4)
73 #define GPIOKEY_BIT_DIRUP (1 << 3)
74 #define GPIOKEY_BIT_DIRLEFT (1 << 2)
75 #define GPIOKEY_BIT_DIRRIGHT (1 << 1)
76 #define GPIOKEY_BIT_DIRDOWN (1 << 0)
78 /* the hotkey combination which starts recovery */
79 #define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
82 static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
86 setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
88 clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
92 static u32 gpio_querykbd(void)
99 im = (immap_t *)CONFIG_SYS_IMMR;
100 gpioregs = &im->gpio;
103 /* query upper row */
104 gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
105 input = in_be32(&gpioregs->gpdat);
106 if ((input & GPIOKEY_COL0_BITMASK) == 0)
107 keybits |= GPIOKEY_BIT_FNLEFT;
108 if ((input & GPIOKEY_COL1_BITMASK) == 0)
109 keybits |= GPIOKEY_BIT_DIRUP;
110 if ((input & GPIOKEY_COL2_BITMASK) == 0)
111 keybits |= GPIOKEY_BIT_FNRIGHT;
113 /* query lower row */
114 gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
115 input = in_be32(&gpioregs->gpdat);
116 if ((input & GPIOKEY_COL0_BITMASK) == 0)
117 keybits |= GPIOKEY_BIT_DIRLEFT;
118 if ((input & GPIOKEY_COL1_BITMASK) == 0)
119 keybits |= GPIOKEY_BIT_DIRRIGHT;
120 if ((input & GPIOKEY_COL2_BITMASK) == 0)
121 keybits |= GPIOKEY_BIT_DIRDOWN;
123 /* return bit pattern for keys */
127 /* excerpt from the recovery's hw_info.h */
129 static int eeprom_diag = 1;
131 struct __attribute__ ((__packed__)) eeprom_layout {
132 char magic[3]; /** 'ifm' */
133 u8 len[2]; /** content length without magic/len fields */
134 u8 version[3]; /** structure version */
135 u8 type; /** type of PCB */
136 u8 reserved[0x37]; /** padding up to offset 0x40 */
137 u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
140 #define HW_COMP_MAINCPU 2
142 static struct eeprom_layout eeprom_content;
143 static int eeprom_was_read; /* has_been_read */
144 static int eeprom_is_valid;
145 static int eeprom_version;
147 #define get_eeprom_field_int(name) ({ \
151 for (idx = 0; idx < sizeof(name); idx++) { \
153 value |= name[idx]; \
158 static int read_eeprom(void)
167 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
168 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
169 (uchar *)&eeprom_content, sizeof(eeprom_content));
171 printf("DIAG: %s() read rc[%d], size[%d]\n",
172 __func__, ret, sizeof(eeprom_content));
181 * check validity of EEPROM content
182 * (check version, length, optionally checksum)
185 eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
186 eeprom_version = get_eeprom_field_int(eeprom_content.version);
189 printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
190 __func__, eeprom_content.magic[0],
191 eeprom_content.magic[1], eeprom_content.magic[2],
192 eeprom_datalen, eeprom_version, eeprom_content.type);
194 if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
196 if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
198 if ((eeprom_version != 1) && (eeprom_version != 2))
200 if (eeprom_content.type != HW_COMP_MAINCPU)
204 printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
209 int mac_read_from_eeprom(void)
214 printf("I2C EEPROM read failed.\n");
218 if (!eeprom_is_valid) {
219 printf("I2C EEPROM content not valid\n");
224 switch (eeprom_version) {
227 mac = (const u8 *)&eeprom_content.macaddress;
231 if (mac && is_valid_ether_addr(mac)) {
232 eth_setenv_enetaddr("ethaddr", mac);
233 printf("DIAG: %s() MAC value [%s]\n",
234 __func__, getenv("ethaddr"));
242 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
243 * which the ADS, Aria or PDM360NG boards are using
244 * (the steps outlined here refer to the Micron datasheet)
246 u32 sdram_init_seq[] = {
247 /* item 6, at least one NOP after CKE went high */
248 CONFIG_SYS_DDRCMD_NOP,
249 CONFIG_SYS_DDRCMD_NOP,
250 CONFIG_SYS_DDRCMD_NOP,
251 CONFIG_SYS_DDRCMD_NOP,
252 CONFIG_SYS_DDRCMD_NOP,
253 CONFIG_SYS_DDRCMD_NOP,
254 CONFIG_SYS_DDRCMD_NOP,
255 CONFIG_SYS_DDRCMD_NOP,
256 CONFIG_SYS_DDRCMD_NOP,
257 CONFIG_SYS_DDRCMD_NOP,
258 /* item 7, precharge all; item 8, tRP (20ns) */
259 CONFIG_SYS_DDRCMD_PCHG_ALL,
260 CONFIG_SYS_DDRCMD_NOP,
261 /* item 9, extended mode register; item 10, tMRD 10ns) */
262 CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
263 CONFIG_SYS_DDRCMD_NOP,
265 * item 11, (base) mode register _with_ reset DLL;
266 * item 12, tMRD (10ns)
268 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
269 CONFIG_SYS_MICRON_BMODE_PARAM,
270 CONFIG_SYS_DDRCMD_NOP,
271 /* item 13, precharge all; item 14, tRP (20ns) */
272 CONFIG_SYS_DDRCMD_PCHG_ALL,
273 CONFIG_SYS_DDRCMD_NOP,
275 * item 15, auto refresh (i.e. refresh with CKE held high);
276 * item 16, tRFC (70ns)
278 CONFIG_SYS_DDRCMD_RFSH,
279 CONFIG_SYS_DDRCMD_NOP,
280 CONFIG_SYS_DDRCMD_NOP,
281 CONFIG_SYS_DDRCMD_NOP,
282 CONFIG_SYS_DDRCMD_NOP,
283 CONFIG_SYS_DDRCMD_NOP,
284 CONFIG_SYS_DDRCMD_NOP,
285 CONFIG_SYS_DDRCMD_NOP,
286 CONFIG_SYS_DDRCMD_NOP,
288 * item 17, auto refresh (i.e. refresh with CKE held high);
289 * item 18, tRFC (70ns)
291 CONFIG_SYS_DDRCMD_RFSH,
292 CONFIG_SYS_DDRCMD_NOP,
293 CONFIG_SYS_DDRCMD_NOP,
294 CONFIG_SYS_DDRCMD_NOP,
295 CONFIG_SYS_DDRCMD_NOP,
296 CONFIG_SYS_DDRCMD_NOP,
297 CONFIG_SYS_DDRCMD_NOP,
298 CONFIG_SYS_DDRCMD_NOP,
299 CONFIG_SYS_DDRCMD_NOP,
300 /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
301 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
302 CONFIG_SYS_DDRCMD_NOP,
304 * item 21, "actually done", but make sure 200 DRAM clock cycles
305 * have passed after DLL reset before READ requests are issued
306 * (200 cycles at 160MHz -> 1.25 usec)
308 /* EMPTY, optional, we don't do it */
311 phys_size_t initdram(int board_type)
313 return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
316 int misc_init_r(void)
322 /* we use bus I2C-0 for the on-board eeprom */
325 /* setup GPIO directions and initial values */
329 * check the GPIO keyboard,
330 * enforced start of the recovery when
331 * - the appropriate keys were pressed
332 * - a previous installation was aborted or has failed
333 * - "some" external software told us to
336 keys = gpio_querykbd();
337 printf("GPIO keyboard status [0x%08X]\n", keys);
338 /* XXX insist in the _exact_ combination? */
339 if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
340 printf("GPIO keyboard requested RECOVERY\n");
342 * refine the logic to detect the first keypress, and
343 * wait to recheck IF it was the recovery combination?
347 s = getenv("install_in_progress");
348 if ((s != NULL) && (*s != '\0')) {
349 printf("previous installation aborted, running RECOVERY\n");
352 s = getenv("install_failed");
353 if ((s != NULL) && (*s != '\0')) {
354 printf("previous installation FAILED, running RECOVERY\n");
357 s = getenv("want_recovery");
358 if ((s != NULL) && (*s != '\0')) {
359 printf("running RECOVERY according to the request\n");
364 setenv("bootcmd", "run recovery");
367 * boot the recovery system without waiting; boot the
368 * production system without waiting by default, only
369 * insert a pause (to provide a chance to get a prompt)
370 * when GPIO keys were pressed during power on
373 setenv("bootdelay", "0");
375 setenv("bootdelay", "0");
377 setenv("bootdelay", "2");
379 /* get the ethernet MAC from I2C EEPROM */
380 mac_read_from_eeprom();
385 /* setup specific IO pad configuration */
386 static iopin_t ioregs_init[] = {
388 offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
389 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
390 IO_PIN_FMUX(1) | IO_PIN_DS(2),
393 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
398 offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
403 offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
404 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
405 IO_PIN_FMUX(1) | IO_PIN_DS(2),
407 { /* SDHC CLK, CMD, D0, D1, D2, D3 */
408 offsetof(struct ioctrl512x, io_control_pata_ior), 6,
409 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
410 IO_PIN_FMUX(1) | IO_PIN_DS(2),
412 { /* GPIO keyboard */
413 offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
417 { /* GPIO DN1 PF, LCD power, DN2 PF */
418 offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
422 { /* GPIO reset AS-i */
423 offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
427 { /* GPIO reset safety */
428 offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
432 { /* GPIO reset netX */
433 offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
438 offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
442 { /* GPIO SD CD, SD WP */
443 offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
448 offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
449 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
450 IO_PIN_FMUX(2) | IO_PIN_DS(2),
452 { /* GPIO AS-i prog, AS-i done, LCD backlight */
453 offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
457 { /* GPIO AS-i wdg */
458 offsetof(struct ioctrl512x, io_control_pci_req2), 1,
462 { /* GPIO safety wdg */
463 offsetof(struct ioctrl512x, io_control_pci_req1), 1,
467 { /* GPIO netX wdg */
468 offsetof(struct ioctrl512x, io_control_pci_req0), 1,
472 { /* GPIO IRQ powerfail */
473 offsetof(struct ioctrl512x, io_control_pci_inta), 1,
477 { /* GPIO AS-i PWRD */
478 offsetof(struct ioctrl512x, io_control_pci_frame), 1,
482 { /* GPIO LED0, LED1 */
483 offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
487 { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
488 offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
493 offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
494 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
495 IO_PIN_FMUX(2) | IO_PIN_DS(2),
497 { /* FEC TX ER, CRS */
498 offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
499 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
500 IO_PIN_FMUX(1) | IO_PIN_DS(2),
502 { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
503 offsetof(struct ioctrl512x, io_control_irq0), 1,
508 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
509 * rdx 3-0, mdio, rx clk
511 offsetof(struct ioctrl512x, io_control_psc0_0), 15,
512 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
513 IO_PIN_FMUX(1) | IO_PIN_DS(2),
515 /* optional: make sure PSC3 remains the serial console */
517 offsetof(struct ioctrl512x, io_control_psc3_4), 1,
518 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
519 IO_PIN_FMUX(1) | IO_PIN_DS(2),
521 /* make sure PSC4 remains available for SPI,
522 *BUT* PSC4_1 is a GPIO kind of SS! */
523 { /* enforce drive strength on the SPI pin */
524 offsetof(struct ioctrl512x, io_control_psc4_0), 5,
529 offsetof(struct ioctrl512x, io_control_psc4_1), 1,
533 /* optional: make sure PSC5 remains available for SPI */
534 { /* enforce drive strength on the SPI pin */
535 offsetof(struct ioctrl512x, io_control_psc5_0), 5,
540 offsetof(struct ioctrl512x, io_control_psc6_0), 1,
541 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
542 IO_PIN_FMUX(1) | IO_PIN_DS(2),
545 offsetof(struct ioctrl512x, io_control_psc6_1), 1,
546 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
547 IO_PIN_FMUX(2) | IO_PIN_DS(1),
550 offsetof(struct ioctrl512x, io_control_psc6_4), 1,
551 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
552 IO_PIN_FMUX(2) | IO_PIN_DS(1),
554 { /* PSC7, part of DIU RGB */
555 offsetof(struct ioctrl512x, io_control_psc7_0), 2,
556 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
557 IO_PIN_FMUX(2) | IO_PIN_DS(1),
559 { /* PSC7, safety UART */
560 offsetof(struct ioctrl512x, io_control_psc7_2), 2,
561 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
562 IO_PIN_FMUX(0) | IO_PIN_DS(1),
564 { /* DIU (part of) RGB[] */
565 offsetof(struct ioctrl512x, io_control_psc8_3), 16,
566 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
567 IO_PIN_FMUX(2) | IO_PIN_DS(1),
569 { /* DIU data enable */
570 offsetof(struct ioctrl512x, io_control_psc11_4), 1,
571 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
572 IO_PIN_FMUX(2) | IO_PIN_DS(1),
574 /* reduce LPB drive strength for improved EMI */
575 { /* LPC OE, LPC RW */
576 offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
580 { /* LPC AX03 through LPC AD00 */
581 offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
586 offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
591 offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
596 offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
604 puts("Board: ifm AC14xx\n");
606 /* initialize function mux & slew rate IO inter alia on IO Pins */
607 iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
612 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
613 void ft_board_setup(void *blob, bd_t *bd)
615 ft_cpu_setup(blob, bd);
617 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */