1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * ids8313.c - ids8313 board support.
10 * Sergej Stepanov <ste@ids.de>
11 * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
17 #include <linux/libfdt.h>
19 DECLARE_GLOBAL_DATA_PTR;
20 /** CPLD contains the info about:
21 * - board type: *pCpld & 0xF0
22 * - hw-revision: *pCpld & 0x0F
23 * - cpld-revision: *pCpld+1
27 char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
28 u8 u8Vers = readb(pcpld);
29 u8 u8Revs = readb(pcpld + 1);
32 switch (u8Vers & 0xF0) {
40 printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
43 printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
44 u8Vers & 0x0F, u8Revs & 0xFF);
51 int fixed_sdram(unsigned long config)
53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
54 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
56 #ifndef CONFIG_SYS_RAMBOOT
57 u32 msize_log2 = __ilog2(msize);
59 out_be32(&im->sysconf.ddrlaw[0].bar,
60 (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
61 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
62 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
66 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
67 * or the DDR2 controller may fail to initialize correctly.
71 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
72 out_be32(&im->ddr.cs_config[0], config);
74 /* currently we use only one CS, so disable the other banks */
75 out_be32(&im->ddr.cs_config[1], 0);
76 out_be32(&im->ddr.cs_config[2], 0);
77 out_be32(&im->ddr.cs_config[3], 0);
79 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
80 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
81 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
82 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
84 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
85 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
87 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
88 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
90 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
91 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
95 /* enable DDR controller */
96 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
97 /* now check the real size */
99 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
105 static int setup_sdram(void)
107 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
108 long int size_01, size_02;
110 size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
111 size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
113 if (size_01 > size_02)
114 msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
123 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
124 fsl_lbc_t *lbc = &im->im_lbc;
127 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
130 msize = setup_sdram();
132 out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
133 out_be32(&lbc->mrtpr, 0x20000000);
136 gd->ram_size = msize;
141 #if defined(CONFIG_OF_BOARD_SETUP)
142 int ft_board_setup(void *blob, bd_t *bd)
144 ft_cpu_setup(blob, bd);
150 /* gpio mask for spi_cs */
151 #define IDSCPLD_SPI_CS_MASK 0x00000001
152 /* spi_cs multiplexed through cpld */
153 #define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
155 #if defined(CONFIG_MISC_INIT_R)
156 /* srp umcr mask for rts */
157 #define IDSUMCR_RTS_MASK 0x04
158 int misc_init_r(void)
161 duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
162 duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
164 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
165 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
167 /* deactivate spi_cs channels */
169 /* deactivate the spi_cs */
170 setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
171 /*srp - deactivate rts*/
172 out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
173 out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
176 gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
181 #ifdef CONFIG_MPC8XXX_SPI
183 * The following are used to control the SPI chip selects
185 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
187 return bus == 0 && ((cs >= 0) && (cs <= 2));
190 void spi_cs_activate(struct spi_slave *slave)
192 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
193 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
195 /* select the spi_cs channel */
196 out_8(spi_base, 1 << slave->cs);
197 /* activate the spi_cs */
198 clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
201 void spi_cs_deactivate(struct spi_slave *slave)
203 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
204 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
206 /* select the spi_cs channel */
207 out_8(spi_base, 1 << slave->cs);
208 /* deactivate the spi_cs */
209 setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);