3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
34 #if defined(CONFIG_LITE5200B)
35 #include "mt46v32m16.h"
37 # if defined(CONFIG_MPC5200_DDR)
38 # include "mt46v16m16-75.h"
40 #include "mt48lc16m16a2-75.h"
44 #ifdef CONFIG_LITE5200B_PM
45 /* u-boot part of low-power mode implementation */
46 #define SAVED_ADDR (*(void **)0x00000000)
49 void lite5200b_wakeup(void)
51 unsigned char wakeup_pin;
52 void (*linux_wakeup)(void);
54 /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
55 * from low power mode */
56 *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
57 __asm__ volatile ("sync");
59 wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
60 if (wakeup_pin & PSC2_4)
63 /* acknowledge to "QT"
64 * by holding pin at 1 for 10 uS */
65 *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
66 __asm__ volatile ("sync");
67 *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
68 __asm__ volatile ("sync");
71 /* put ram out of self-refresh */
72 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
73 __asm__ volatile ("sync");
74 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
75 __asm__ volatile ("sync");
76 *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
77 __asm__ volatile ("sync");
78 udelay(10); /* wait a bit */
80 /* jump back to linux kernel code */
81 linux_wakeup = SAVED_ADDR;
82 printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
83 (unsigned long)linux_wakeup);
87 #define lite5200b_wakeup()
90 #ifndef CONFIG_SYS_RAMBOOT
91 static void sdram_start (int hi_addr)
93 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
95 /* unlock mode register */
96 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
97 __asm__ volatile ("sync");
99 /* precharge all banks */
100 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
101 __asm__ volatile ("sync");
104 /* set mode register: extended mode */
105 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
106 __asm__ volatile ("sync");
108 /* set mode register: reset DLL */
109 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
110 __asm__ volatile ("sync");
113 /* precharge all banks */
114 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
115 __asm__ volatile ("sync");
118 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
119 __asm__ volatile ("sync");
121 /* set mode register */
122 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
123 __asm__ volatile ("sync");
125 /* normal operation */
126 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
127 __asm__ volatile ("sync");
132 * ATTENTION: Although partially referenced initdram does NOT make real use
133 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
134 * is something else than 0x00000000.
137 phys_size_t initdram (int board_type)
143 #ifndef CONFIG_SYS_RAMBOOT
146 /* setup SDRAM chip selects */
147 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
148 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
149 __asm__ volatile ("sync");
151 /* setup config registers */
152 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
153 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
154 __asm__ volatile ("sync");
158 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
159 __asm__ volatile ("sync");
162 /* find RAM size using SDRAM CS0 only */
164 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
166 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
174 /* memory smaller than 1MB is impossible */
175 if (dramsize < (1 << 20)) {
179 /* set SDRAM CS0 size according to the amount of RAM found */
181 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
183 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
186 /* let SDRAM CS1 start right after CS0 */
187 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
189 /* find RAM size using SDRAM CS1 only */
192 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
195 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
204 /* memory smaller than 1MB is impossible */
205 if (dramsize2 < (1 << 20)) {
209 /* set SDRAM CS1 size according to the amount of RAM found */
211 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
212 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
214 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
217 #else /* CONFIG_SYS_RAMBOOT */
219 /* retrieve size of memory connected to SDRAM CS0 */
220 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
221 if (dramsize >= 0x13) {
222 dramsize = (1 << (dramsize - 0x13)) << 20;
227 /* retrieve size of memory connected to SDRAM CS1 */
228 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
229 if (dramsize2 >= 0x13) {
230 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
235 #endif /* CONFIG_SYS_RAMBOOT */
238 * On MPC5200B we need to set the special configuration delay in the
239 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
240 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
242 * "The SDelay should be written to a value of 0x00000004. It is
243 * required to account for changes caused by normal wafer processing
248 if ((SVR_MJREV(svr) >= 2) &&
249 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
251 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
252 __asm__ volatile ("sync");
257 return dramsize + dramsize2;
260 int checkboard (void)
262 #if defined (CONFIG_LITE5200B)
263 puts ("Board: Freescale Lite5200B\n");
265 puts ("Board: Motorola MPC5200 (IceCube)\n");
270 void flash_preinit(void)
273 * Now, when we are in RAM, enable flash write
274 * access for detection process.
275 * Note that CS_BOOT cannot be cleared when
276 * executing in flash.
278 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
281 void flash_afterinit(ulong size)
283 if (size == 0x800000) { /* adjust mapping */
284 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
285 START_REG(CONFIG_SYS_BOOTCS_START | size);
286 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
287 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
292 static struct pci_controller hose;
294 extern void pci_mpc5xxx_init(struct pci_controller *);
296 void pci_init_board(void)
298 pci_mpc5xxx_init(&hose);
302 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
304 void init_ide_reset (void)
306 debug ("init_ide_reset\n");
308 /* Configure PSC1_4 as GPIO output for ATA reset */
309 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
310 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
312 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
315 void ide_set_reset (int idereset)
317 debug ("ide_reset(%d)\n", idereset);
320 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
321 /* Make a delay. MPC5200 spec says 25 usec min */
324 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
329 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
331 ft_board_setup(void *blob, bd_t *bd)
333 ft_cpu_setup(blob, bd);
337 int board_eth_init(bd_t *bis)
339 cpu_eth_init(bis); /* Built in FEC comes first */
340 return pci_eth_init(bis);